以可繞度為導向考慮障礙物之巨集電路擺置

為了加速產品上市速度，矽智財 (Intellectual Property) 巨集電路已被廣泛地使用在先進系統單晶片 (System-on-a-Chip) 中。其中，部分的巨集電路因為製程及其他設計的需求而被限制擺放在特定位置。對於巨集電路擺置而言，這些須預置擺放的巨集電路將被視為障礙物，且不得與其他巨集電路或標準單元重疊。在本篇論文中，我們提出一個新的環形堆積樹 (CP-tree) 表示法來處理預置擺放巨集電路的問題。 CP-tree 藉由預置擺放巨集電路來快速且有效地擺置巨集電路於晶片四周，並且保留完整空間來擺置標準單元。此外，巨集電路的位置與方向會顯著影響標準單元放置及繞線擁塞程度。因此，不像其他的巨集電路擺置器只考慮巨集電路之間的連線而忽略標準單元之可繞度，我們提出一個全新的以可繞度為導向的繞線模型 (Routability-Driven Wirelength Model) 來降低繞線時的壅塞程度。此繞線模型不僅可以快速估計巨集電路與標準單元之間的連線長度，並且可將巨集電路直通矽晶穿孔 (Macro Porosity) 反映在此模型上來增加晶片可繞度。實驗結果顯示出，我們所提出的巨集電路擺置演算法方法相較於先前的巨集電路擺置器，可以有效地得到最好的電路擺置結果。並且，藉由業界的實際電路實驗結果亦顯示出，我們的方法可以得到最好的可繞度且最能接近工程師手動擺置的結果。

關鍵字

實體設計；擺置；巨集電路；障礙物；可繞度

並列摘要

To speed up the time to market for system-on-a-chip (SoC), a chip usually contains tens or even hundreds of intellectual property (IP) macros (e.g., analog blocks, embedded memories). Some of those macros, namely pre-placed macros, need to be placed at speci ed locations for di erent issues, such as power, ther- mal, and the connections with IO pads. In macro placement, the pre-placed macros are treated as blockages and not allowed to overlap with other macros. Hence, for complex designs with many pre-placed macros, it would incur the di culties of nding a non-overlapping placement result. To handle the blockages and prevent overlaps among macros, we propose a new circular-packing tree (CP-tree) oorplan representation for our macro placement algorithm. A CP-tree could exibly pack movable macros toward corners or toward pre-placed macros along chip boundaries circularly to optimize the macro positions and preserve a complete placement re- gion for standard-cell placement. Moreover, the macro positions and orientations would signi cantly a ect the wirelength and routing congestion in the standard-cell placement and routing stages, but most of existing macro placers only consider the interconnections among macros. Therefore, a routability-driven wirelength model is presented to fast estimate the wirelength among macros and standard cells and to consider the macro porosity e ect for better routability. Experimental results show the e ectiveness and e ciency of our macro placement algorithm. Compared with state-of-the-art academic macro placers, our algorithm obtains the best wire- length results in ISPD 2006 placement benchmarks. Furthermore, for real industry benchmarks, our algorithm can achieve the shortest routed wirelength results as competitive as manual designs, compared with leading academic mixed-size placers.

並列關鍵字

physical design ； placement ； macro ； blockage ； routability

參考文獻

[3] U. Brenner, M. Struzyna, and J. Vygen. BonnPlace: Placement of leading-edge chips by advanced combinatorial algorithms. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 27(9):1607-1620, September 2008.

[4] T. F. Chan, J. Cong, and K. Sze. Multilevel generalized force-directed method for circuit placement. In Proceedings of ACM International Symposium on Physical Design, pages 185-192, 2005.

[8] T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang. NTUplace3: An analytical placer for large-scale mixed-size designs with pre-placed blocks and density constraints. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 27(7):1228-1240, July 2008.

[13] S. Dhamdhere, N. Zhou, and T.-C. Wang. Module placement with pre-placed modules using the corner block list representation. In IEEE International Symposium on Circuits and Systems, volume 1, pages I-349-I-352, 2002.

[14] P.-N. Guo, C.-K. Cheng, and T. Yoshimura. An O-tree representation of non-slicing foorplan and its applications. In Proceedings of ACM/IEEE Design Automation Conference, pages 268-273, 1999.

國際替代計量

以可繞度為導向考慮障礙物之巨集電路擺置

全文下載

主題瀏覽