應用時間特徵函式之針對延遲缺陷自動測資產生方法

針對延遲缺陷之自動測資產生方法(ATPG)是積體電路(IC)設計流程中重要的品質控制步驟。隨著電路尺寸的縮小及操作頻率的增加,電路延遲上的一點小變化將會嚴重地影響電路行為。延遲錯誤主要是由電路製造過程中的瑕疵所造成並且會導致電路運作上的錯誤,對於性能較好的電路,小延遲缺陷造成的影響更是特別值得注意及研究。測試延遲錯誤主要分成兩種方法:非時間感知型及時間感知型。非時間感知型自動測資產生的計算速度較快但對於小延遲缺陷無法產生品質夠佳的測資;時間感知型的自動測資產生可以改進此項缺點,然而對於大型電路來說它的計算複雜度太高而難以實行。這篇論文提出一項時間感知型的自動測資產生方法,其利用時間特徵函式將原問題轉化成布林可滿足性問題並求解之,而時間特徵函式是目前最快的功能性時序分析方法之一。這項自動測資產生方法可被應用在組合電路及序向電路上,它在精確度及效率之間達到很好的平衡。透過實驗比較,可以發現我們提出的方法在執行時間及錯誤涵蓋率都比先前同樣利用布林可滿足性問題求解的時間感知型自動測資產生方法更佳,另外,我們也提出了幾項可以使自動測資產生有更好測資品質及效率的技術。最後,我們的方法可以與商業工具結合並增加測資品質。

關鍵字

自動測資產生；延遲錯誤；功能性時序分析；布林可滿足性問題；小延遲缺陷；時間特徵函式

並列摘要

Automatic test pattern generation (ATPG) for delay defects is an essential quality control step in integrated circuit (IC) design flow. With feature dimensions shrinking and operation frequency increasing, small changes on circuit delay may seriously affect the circuit behavior. Delay faults are caused by the intrinsic imperfection of manufacturing process and may result in behavior deviation from correct operation. For high performance circuits, the influence of small delay defects (SDDs) is particularly significant. There are two kinds of prior ATPG methods, including timing-unaware and timing-aware ATPG. Timing-unaware ATPG is fast but can not provide high quality patterns for testing SDDs. Timing-aware ATPG addresses the shortcoming of timing-unaware ATPG, but is computationally too expensive for large circuits. This thesis proposes a viable timing-aware ATPG method based on a satisfiability (SAT) formulation using timed characteristic functions (TCFs), which is considered as one of the fastest functional timing analysis (FTA) techniques. The approach can be applied on both combinational and sequential circuits. It provides a balanced trade-off between accuracy and efficiency. Experimental results show promising runtime and fault coverage improvements over prior SAT-based timing-aware ATPG methods. We also implement some enhancement techniques to improve ATPG efficiency and test quality. In addition, our method provides a nice complement to commercial tools in enhancing test quality.

並列關鍵字

Automatic Test Pattern Generation ； Delay Fault ； Functional Timing Analysis ； Satisfiability Problem ； Small Delay Defect ； Timed Characteristic Function

參考文獻

[4] M. Bushnell and V. Agrawal. Essentials of Electronics Testing. Kluwer Pub- lishers, 2000.

[1] M. E. Amyeen, S. Venkataraman, A. Ojha, and S. Lee. Evaluation of the Quality of N-Detect Scan ATPG Patterns on a Processor. In Proc. International Test Conference (ITC), pp. 669-678, 2004.

[5] H.-C. Chen and D. Du. Path Sensitization in Critical Path Problem. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 12(2): 196-207, 1993.

[7] K.-T. Cheng. and H.-C. Chen. Generation of High Quality Non-Robust Tests for Path Delay Faults. In Proc. Design Automation Conference (DAC), pp. 365-369, 1994.

[12] P. Goel. An Implicit Enumeration Algorithm to Generate Tests for Combina- tional Logic Circuits. IEEE Trans. on Computers, 100(3): 215-222, 1981.

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應用時間特徵函式之針對延遲缺陷自動測資產生方法

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