在 40 奈米製程使用2.5 對1 多工器之串接式傳送機

A 20mW Serializing Transmitter with 2.5:1 Multiplexers in 40nm Technology

林柏境(Bo-Jing Lin)

指導教授 ： 李泰成

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2015年)

https://doi.org/10.6342/NTU.2015.10521

摘要

2007年底，IEEE P802.3ba正式被提出，其定義了40 GbE與100 GbE的規範，目的是將 IEEE 802.3的協定延伸至40 Gbps與100 Gbps的操作速度，同時符合現行協定與傳輸距離要求。IEEE P802.3ba定義之 100GbE，100GbE定義將十通道10 Gbps 轉換為四通道 25 Gbps輸出並輔以波長分割多工轉換(Wavelength Division Multiplexing)來達成高速傳輸之目的。在通訊傳輸中，因為傳輸線通道成本相當昂貴，通常希望在單一通道內能傳送更高頻資料的，故需要將資料做串接的電路，以減少通道的成本。在100GbE的傳送機系統，需要將十通道10 Gbps 轉換為 四通道25 Gbps 的介面之中，因為沒有小數倍的多工器，故需先將十通道10 Gbps降頻，再升頻至四通道 25 Gbps，例如十通道10 Gbps透過1:2解多工器轉換為二十通道5 Gbps，再利用5:1多工器轉換為四通道25 Gbps，這過程相當繁複且消耗硬體資源。此論文為一串接式傳送機使用2.5:1多工器，我們不需要將資料先降頻再升頻以減少硬體的消耗和能源的損耗，由於使用小數倍的多工器架構，我們可以只使用單一頻率時脈來簡化時脈產生器，此傳送機使用40奈米的製程，此傳送機實現傳送雙通道25Gbps，傳送機只消耗25mW在VDD等於0.9V之下。

關鍵字

串接式傳送機 ； 小數倍多工器

並列摘要

At the end of 2007 year, IEEE P802.3ba is generated officially. It defines the specification of 40 GbE and 100 GbE. The purpose is to extend the operation speed of the IEEE 802.3 agreement to 40 Gbps and 100 Gbps, and at the same time it also accords the current agreement and the demand of transmission distance. At the definition of IEEE P802.3ba 100GbE, the 100GbE is used four channels of 25 Gbps output with wavelength division multiplexing to achieve the purpose of high speed transmission. At communication transmission, because the cost of transmission line channel is very expensive, we usually hope to transmit higher frequency data in single channel. Therefore, it is necessary to do data serial circuit to reduce the cost of channel. At the 100GbE transmitter system, it needs to transfer ten channels of 10Gb/s to four channels of 25Gbps at the interface. Because it didn’t exist a fractional multiplexer, we need convert down frequency of ten channels 10Gbps and convert up to four channels 25Gbps. For example, we use 1:2 DEMUX (demultiplexer) to convert down ten channels of 10Gb/s to twenty channels of 5Gb/s, and then we use 5:1 MUX to convert up twenty channels of 5Gbps to four channels of 25Gbps. The process is quite complicated and wasting the device area. The thesis is a serial transmitter with 2.5 to 1 multiplexer. We don’t need to convert data frequency up and down, and it would reduce device area and power consumption. Due to use the architecture of fractional multiplexer, we can just use the single frequency of clock to simply clock generator. The transmitter is used 40 nm technology. The transmitter is implemented to transfer two channels of 25Gbps. The transmitter only dissipates 25 mW at VDD 0.9V.

並列關鍵字

serial transmitter ； fractional multiplexer

參考文獻

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