透過您的圖書館登入
IP:52.91.177.91
  • 學位論文

固液擴散接合在3D IC封裝製程之應用及其可靠度驗證

The Application and Reliability of Solid-Liquid Interdiffusion Bonding Technology in 3D IC Packages

指導教授 : 莊東漢
若您是本文的作者,可授權文章由華藝線上圖書館中協助推廣。

摘要


隨著電子產品輕薄短小的趨勢潮流,對於產品可靠度的要求越來越嚴苛,尤其是目前炙手可熱的3D IC、高功率模組及無芯覆晶封裝,更突顯出高功率及高密度封裝的苛刻要求。對於這類型的構裝技術,高可靠度與壽命就顯得相當重要。本研究以兩個章分別探討3D IC微凸塊C2C封裝技術與可靠度及無芯覆晶載板board-level封裝技術與可靠度,在這兩個技術中,underfill扮演著極重要的材料角色,能降低矽晶片與基板的熱膨脹係數的不匹配。由於underfill特性深深影響著覆晶封裝的可靠度特徵,挑選出適合的underfill將是影響產品壽命的其中一個關鍵因子。 本研究對於3D IC微接點構裝技術,首先評估兩款underfill對可靠度特性的影響,以Cu/Ni/Sn2.5Ag微凸塊製作的微接點為實驗載具,透過數值分析模擬等效彈性應變,歸納出undrfill特性與可靠度的關聯性。接著,將實際組裝的樣品進行溫度循環測試,得到失效樣品數量,從而計算出樣品的壽命。根據數值分析與溫度循環測試的結果,選出適合用於3D IC封裝的underfill材料的特性。完成underfill評估作業後,再使用Cu/Ni/Sn2.5Ag及Cu/Sn兩種微凸塊作為實驗載具,將兩種載具分別以熱壓接合(TCB)與傳統迴銲製程完成接合。實驗規劃是以兩種微凸塊結構搭配兩種組裝方式製作出4種實驗載具,使用適合的underfill進行間隙填充。完成的4種實驗載具以溫度循環測試可靠度,統計載具在不同循環次數的失效數量,從而算出載具的壽命。挑選出失效載具進行微結構分析,解釋失效原因與模式。 完成3D IC微接點結構與可靠度驗證,接著評估3D IC封裝載具的載板級(board-level)封裝,本研究使用ANSYS軟體來研究封裝級(package-level)和載板級(board-level)的無芯覆晶封裝(coreless flip chip package, CFCP)在溫度循環過程產生的應力/應變行為。再以實際的無芯載板覆晶封裝為載具,探討board-level封裝技術與可靠度。載具製作是將17 mm *17 mm的矽晶片組裝到6層PI無芯載板,銲接凸塊材料為Sn37Pb,組裝製程採用氮氣迴銲製程。迴銲完成凸塊接合後,使用氨基underfill進行隙縫填膠,underfill固化條件為150℃烘烤1小時。接著將SAC305錫球植到載板底部的銲墊,再將此載板組裝到印刷電路板,即完成無芯載板覆晶封裝。最後,將無芯覆晶封裝載具進行溫度循環,統計載具在不同循環次數的失效數量,從而算出載具的壽命。挑選出失效載具進行微結構分析,解釋失效原因與模式。

並列摘要


Due to electronic products trend towards light, thin, short, and small, the reliability requirement is more and more higher especially for high power and high density package such as 3D IC, high power module and coreless flip chip package. As the package technology mentioned above, high reliability and characteristic life of metal joint are extremely important. In this paper, we will focus on energy to discuss the rilability of 3D IC package and the board-level reliability of the coreless flip chip package. However, underfill plays as the most important material to enhance the reliability of flip chip package, by reducing the mismatch of coefficient of thermal expansion (CTE) between silicon chip and substrate. To select a compatible underfill material is important because the reliability characteristics of flip chip package were significantly affected by different material properties. Regarding the micro joint technology of 3D IC in this paper, two kinds of underfill were option to evaluate the reliability characteristics of 3D IC flip chip package. A 3D finite element analysis model was established by ANSYS 12.0 software to study the stress / strain contours of the microjoints sealed by various underfill materials under temperature cycling. Moreover, temperature cycling test (TCT) was chosen to evaluate the reliability of the assemblies which were survived after the preconditioning test, and the relationship between the failure rate and the number of cycles. According to the results of simulation and experiments, we choose the compatible underfill material for the following experiments. Two kinds of different microbump structures were used as the test vehicle. The microbumps were with a pitch size of 20

參考文獻


[89] R. W. Yang, Y. W. Chang, C. Chen, T. C. Chang, C. J. Zhan and J. Y. Juang, “Microstructure Evolution in Microbumps for 3D-IC Packaging,” Proceedings of International Microsystems Packaging Assembly and Circuits Technology Conference, pp. 1-4, 2010.
[90] R. W. Yang, Y. W. Chang, C. Chen, T. C. Chang, C. J. Zhan and J. Y. Juang, “Agglomeration of Ag3Sn Compound in Microbumps during Reflow for 3D-IC Packaging,” Proceedings of International Microsystems Packaging Assembly and Circuits Technology Conference, pp. 1-4, 2010.
[31] Printed Circuits Handbook, Editor Clyde F. Coombs, Jr., 4th edition, McGraw-Hill., New York, 1995.
[100] T. C. Chang, R. S. Cheng, P. C. Chang, Y. P. Hung, and J. Y. Chang,“Reliability characterization of 20 μm pitch microjoints assembly by a conventional reflow technique,” in Proc. Int. Conf. Electron. Packag., 2011, pp. 221–226.
[2] K. Sakuma, P. S. Andry, C. K. Tsang, K. Sueoka, Y. Oyama, C. Patel, B. Dang, S. L. Wright, B. C. Webb, E. Sprogis, R. Polastre, R. Horton and J. U. Knickerbocker, “Characterization of stacked die using die-to-wafer integration for high yield and throughput,” in Proc. Electron. Compon. Technol. Conf., Lake Buena Vista, FL, May 2008, pp. 18–23.

延伸閱讀