使用切換偏壓技術之數位倍頻延遲鎖定迴路與具有頻寬校正之數位鎖相迴路

Digital Multiplying Delay-Locked Loop Using Switched Biasing Technique and Digital Phase-Locked Loop with Bandwidth Calibration

蔣季寰(Chi-Huan Chiang)

指導教授 ： 劉深淵

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2014年)

https://doi.org/10.6342/NTU.2014.10582

摘要

這篇論文的主題主要分為兩個部分，第一部分我們實現了一個數位倍頻延遲鎖定迴路搭配切換偏壓技術。我們所提出的選擇邏輯以及除頻器可關掉的架構都可以降低電路的功率消耗。使用切換偏壓技術的數位控制振盪器可以減少低頻相位雜訊，此電路實現於40奈米製程，其面積為0.0088 mm2，在1050 MHz頻率量測到的方均根抖動為2.68 ps，功率消耗為1.51 mW。
第二部分實現了一個具有頻寬校正之數位Bang-Bang鎖相迴路，此電路可以不受環境、製程變異影響，我們採用線性模型去分析此電路的頻寬。所提出的的頻寬校正電路使用數位加法器、減法器以及比較器去取代佔面積的數位除法器，達到小面積的目標。此電路實現於40奈米製程，其面積為0.0049 mm2，在5 GHz頻率量測到的方均根抖動為1.242 ps，功率消耗為3.34 mW。

關鍵字

時脈產生器

並列摘要

This thesis consists of two parts. The first part implement a digital multiplying delay-locked loop (DMDLL) using switched biasing technique. This DMDLL uses the proposed select logic and its main divider can be turned off to reduce the power consumption. The digitally-controlled oscillator (DCO) uses the switched biasing technique to reduce the low-frequency phase noise. This DMDLL is fabricated in 40-nm CMOS technology and its active area is 0.0088 mm2. The integrated RMS jitter is 2.68 ps and the power consumption is 1.51mW at the output frequency of 1050MHz.
The second part implements a digital bang-bang phase-locked loop (BBPLL) with bandwidth calibration. It is presented to against the process, voltage, and temperature (PVT) variations. A linearized model of the BBPLL is constructed to analyze the bandwidth of the BBPLL. The proposed bandwidth calibration circuit adopts the adders, the subtractors, and the comparators to replace the area-consuming division circuit, which reduces the area overhead. This BBPLL was fabricated in 40-nm CMOS technology with an active area of 0.0049 mm2. The output frequency is 5 GHz. The integrated RMS jitter is 1.242 ps, and the power consumption is 3.34 mW.

並列關鍵字

Clock Generators

參考文獻

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