在限制隨機驗證中的高速廣義分佈測試模式產生器

A High-Throughput and General-Distribution Pattern Generator for Constrained Random Verification

吳柏翰(Bo-Han Wu)

指導教授 ： 黃鐘揚

國立臺灣大學/電機資訊學院/電子工程學研究所/博士(2014年)

https://doi.org/10.6342/NTU.2014.01331

摘要

現今為了驗證某些系統性的性質，限制隨機驗證方法(CRV)逐漸成為主流。主要原因是CRV擁有更高的效率和更好的擴展性。在此驗證方法中，驗證工程師只須撰寫限制式來表達待驗證的環境，而不需繁瑣地描述每個模擬測試的數值。當撰寫完這些限制式後，可透過限制式求解器來求解這些限制式，產生滿足限制的測試數值，進而模擬整個電路。為了保證主要的驗證可以花費於模擬電路和確認觀測的性質對錯上，產生符合限制式之測試數值的過程只能耗費相對少量的計算資源。另一方面，為了保證最好的驗證品質，VDL標準要求產生的模擬數值分布必須要均勻或者是符合驗證工程師所設定的機率分布。
在此研究中，我們提出一個限制求解技術來加速模擬數值的產生過程。而此法我們簡稱為RSSDE技術。我們主要著重在克服以下三個挑戰：1) 產生模擬數值以及滿足機率分步的權衡 2) 驗證限制式中包含變數順序的條件 3) 驗證環境中包含多種限制式的不同組合。以上這些挑戰皆在業界驗證環境中時常出現，像是出現於UVM或VVM的驗證環境中。而我們提出的技術保證加速產生過程，且同時滿足驗證工程師所要求的模擬數值機率分布。實驗結果亦顯示，在與業界所開發的系統比較，我們所提出的技術擁有較高速率的模擬數值產生優勢。

關鍵字

功能性驗證 ； CRV ； SystemVerilog ； 樣式分布 ； 限制求解

並列摘要

Nowadays, Constrained Random Verification (CRV) methodology is becoming the mainstream to verify system-wide properties for the advantage of its scalability and efficiency. Verification engineers implement verification scenario by writing constraints instead of explicitly specifying simulation patterns. A constraint solver is then applied to solve those constraints and generate feasible stimuli to exercise the design. To assure that the majority of the verification efforts are spent on the simulation of the design and the validation of the assertions/monitors, it is required that the pattern generation process should be computationally inexpensive and thus only consume a small fraction of the computing resource. On the other hand, to ensure the best verification quality, it is specified in the VDL manual that the distribution of the generated stimuli should be even or meet the user-specified distribution.
In this dissertation, we propose a constrained pattern generation technique which is called “Range-Splitting and Solution-Density Estimation (RSSDE)” to accelerate the pattern generation processes. We focus on conquering three practical challenges: 1) the tradeoff between pattern generation speed and distribution requirement 2) testbench with solving-order constraints 3) testbench with multiple constraint sets. The above three issues frequently appear in real verification environment like UVM and VVM. Furthermore, we guarantee that the generated patterns satisfy the distribution requirement with the benefits of pattern generation acceleration. The experimental results demonstrate the robustness and efficiency of our framework when compared to a commercial tool.

並列關鍵字

functional verification ； CRV ； SystemVerilog ； pattern distribution ； constraint solving ； solving-order constraints

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