考慮最小植入層面積及標準元件間距之細部擺置

A Minimum-Implant-Area-Aware Detailed Placement Algorithm with Spacing Constraints

曾楷涵(Kai-Han Tseng)

指導教授 ： 張耀文

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2015年)

https://doi.org/10.6342/NTU.2015.10576

摘要

同時優化晶片效能及降低功率消耗一直是現今電路設計中難解的問題之一，為了權衡這兩項工作，現今的製程多提供不同臨界電壓的標準元件來設計電路，以達到高效能、低漏電流的目標。一般而言，不同臨界電壓的標準元件可以透過控制植入層上的摻雜濃度而製造，然而，隨著製程的演進，標準元件尺寸的縮小，晶片設計的限制變得日益嚴峻，如果一個低臨界電壓或是高臨界電壓的標準元件的寬度太小，其植入層將會違反最小植入層面積這個限制條件，當一個標準元件違反此條件，我們必須將其周圍的標準元件推開以預留空間，或是將其與同樣臨界電壓的標準元件相鄰地擺置在一起，因此，最小植入層面積這個限制條件可以被歸納為一個擺置的問題。由於最小植入層面積會大幅度地降低電路擺置的靈活性，因此，在這篇論文裡，我們提出了一個考慮最小植入層面積及標準元件間距之細部擺置演算法，在演算法中，我們透過將違反最小植入層面積的標準元件群聚，以將其轉化成一個以群聚為基礎的擺置問題，並延伸傳統細部擺置演算法來處理此問題。為了實現此方法，我們推導出一個找到群聚元件的最佳區域的方法，並提出一套以網路流為基礎的群聚以及分解群聚的演算法，來達成攪動群聚卻能維持群聚解的目的，此外，我們更提出了一套考慮最小植入層面積的標準元件翻轉演算法來進一步最小化晶片的面積，實驗結果顯示，跟前人的研究相比，本論文所提出的演算法不僅能同時最小化晶片的線長以及面積，並且能在不同的晶片上都有穩定的結果。

關鍵字

實體設計 ； 電路擺置 ； 漏電流 ； 晶片效能 ； 植入層面積

並列摘要

Simultaneous timing and power optimization is often a tough task in modern VLSI design flow. To balance these two tough tasks, modern designs often apply multiple threshold voltage (multi-VT) cells to achieve low leakage and high performance requirements. However, as feature sizes decrease, design rules have become more restricted. A low VT or high VT cell having too small width may violate the minimum implant area (MIA) constraint on its implant layers. To solve MIA violations, we may need to shift the neighboring cells to preserve more whitespace or abut the violation cells with the same VT cells. Therefore, the MIA constraint has emerged as a new challenge for circuit placement problem. Because the MIA constraint may significantly limit the placement flexibility, in this thesis, we propose an MIA-aware detailed placement algorithm to effectively solve the placement problem with the MIA constraint. The main idea of this algorithm is to cluster violation cells with the same VT cells to generate a cluster-based placement, and then extend cell-based detailed placement algorithms to cluster-based detailed placement algorithms to solve this problem. Because the solution quality may be affected substantially by the clustering solution, we propose a cluster-based optimal region to minimize the wirelength and solve MIA violations simultaneously, and develop a network-flow-based clustering and declustering algorithm to perturb clusters while maintaining the solution quality. To further minimize the design area, an MIA-aware cell flipping algorithm is also presented. Experimental results show that our proposed algorithms outperform existing work on both wirelength and design area, and is very robust for different multi-VT designs and MIA constraints.

並列關鍵字

Physical Design ； Placement ； Leakage Power ； Timing Optimization ； Implant Area

參考文獻

[1] Cadence, Inc. LEF/DEF 5.3 to 5.7 exchange format, http://www.si2.org/openeda.si2.org/projects/lefdef.

[2] ISPD 2014 Detailed Routing-Driven Placement Contest, http://www.ispd.cc/contests/14/ispd2014 contest.html.

[3] ISPD 2015 Detailed Routing-Driven Placement Contest, http://www.ispd.cc/contests/15/ispd2015 contest.html.

[4] M. Anis, M. Mahmoud, M. Elmasry, and S. Areibi, “Dynamic and leakage

power reduction in MTCMOS circuits using an automated efficient gate clustering technique,” in Proceedings of ACM/IEEE Design Automation Conference, pp. 480–485, June 2002.