應用於生醫系統之低功耗逐漸趨近式類比至數位轉換器之設計

Design of Low Power SAR Analog-to-Digital Converters for Biomedical System Applications

吳彥霆(Yen-Ting Wu)

指導教授 ： 呂學士

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2017年)

https://doi.org/10.6342/NTU201703507

摘要

本篇論文提出兩個適用於逐漸趨近式類比至數位轉換器(SAR ADC)的類比及混合電路設計技術，並已經由晶片下線與量測結果驗證這些技術的實用性。
第一個技術是使用混合式的單位電容。基於先前的設計，本篇論文使用了兩種不同的單位電容，將10-bit 解析度之SAR ADC 提升至12-bit　。且由於前10-bit的電容陣列之容值大小並沒有隨之改變，因此相較於使用單一單位電容之電路架構，本技術並不會增加額外的晶片面積（小於1%），電容切換時的功耗也幾乎沒有增加。採用此技術的類比至數位轉換器在1伏特的操作電壓下，其量測之功率消耗為10.55μW，有效位元數為10.827 bits。其品質因數為29.0 fJ/conversion-step。
第二個技術是次階逐漸趨近式類比至數位轉換器。本技術在電路架構中加入了一個解析度較低的SAR ADC，用以預先得知前n個位元的粗略值，再經過一個判定切換可否省略的邏輯電路，來達到省電的效果。採用此技術的類比至數位轉換器在1伏特的操作電壓下，其模擬之功率消耗為3.683μW，有效位元數為11.818 bits。其品質因數為5.099 fJ/conversion-step。
此兩個設計都是在0.18μm 1P6M CMOS technology製作的。

關鍵字

逐漸趨近式 ； 類比至數位轉換器 ； 數位錯誤補償 ； 混合式單位電容 ； 次階逐漸趨近式類比至數位轉換器

並列摘要

This thesis presents two analog and mixed-signal circuit design techniques for successive-approximation register (SAR) analog-to-digital converters (ADCs). According to the measurement results of the experimental prototypes, the presented techniques are verified.
The first technique is hybrid unit capacitors. Comparing to last work [1], the resolution bit has been enhanced by adding extra capacitor arrays with an additional smaller unit capacitor. This relevant prototype SAR ADC consumes 10.55μW at 1-V supply, and the effective number of bit (ENOB) is 10.827 bits. The resultant figure of merit (FoM) is 29.0 fJ/conversion-step by measurement results.
The second technique is applying a sub-ranged SAR ADC. By adding a 5-bit sub-ranged SAR ADC to make a pre-decision of the first 5 bits, the switching power of system could be reduced by half. This relevant prototype SAR ADC consumes 3.683μW at 1-V supply, and the ENOB is 11.818 bits. The resultant FoM is 5.099 fJ/conversion-step by simulation results.
Both of the prototypes are implemented in the 0.18μm 1P6M CMOS technology.

並列關鍵字

successive-approximation register ； analog-to-digital converters ； digital error correction ； hybrid unit capacitor ； sub-ranged SAR ADC

參考文獻

[7] C. C. Liu, S. J. Chang, G. Y Huang, Y Z. Lin, C. M. Huang, C. H. Huang, L. Bu, and C. C. Tsai, "A 10b IOOMS/s 1.13mW SAR ADC with Binary-Scaled Error Compensation," in IEEE International Solid-State Circuits Conference Digest of Technical Papers, 2010, pp. 386–387.

[10] C. C. Liu, S. J. Chang, G. Y. Huang, and Y. Z. Lin, “A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13 μm CMOS process,” in IEEE Symp. VLSI Circuits Dig., Jun. 2009, pp. 236–237.

[8] H. W. Chang, “A Low Power Analog-to-Digital Converter for ECG Signal,” National Taiwan University MS Thesis, 2012.

[2] C. C, Liu, S. J. Chang, G. Y. Huang, and Y Z. Lin, "A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure," IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 731-740, Apr. 2010.

[3] S. H. Cho, C. K. Lee, J. K. Kwon, and S. T. Ryu, "A 550-µw 10-b 40-MS/s SAR ADC with Multistep Addition-Only Digital Error Correction," IEEE Journal of Solid-State Circuits, vol. 46, no. 8, pp. 1881-1892, Aug. 2011.