考慮電源供應雜訊之動態時序分析器

Power-Supply-Noise-Aware Dynamic Timing Analyzer

謝弘毅(Hung-Yi Hsieh)

指導教授 ： 李建模

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2014年)

https://doi.org/10.6342/NTU.2014.01768

摘要

當測試超大型積體電路晶片時，由於電壓降和電感電壓的影響，電源供應雜訊會導致良率損失。在這篇論文中，我們提出一個考慮電源供應雜訊之動態時序分析器。我們提出的分析器提供合理的準確度和比現存工具還快的速度。因為我們提出的方法是基於線性函數而不是解非線性函數，所以是非常可調整的。實驗結果顯示：在小電路中，與HSPICE相比的誤差小於1%；在大電路中，我們達到比NANOSIM快八倍的速度。我們使用此分析器在一個有一百萬個邏輯閘的測試電路上，並且從三萬一千個測試向量中辨別出369個時序違規的測試向量，這是傳統方法很難找得到的。

關鍵字

電源供應雜訊 ； 電壓降 ； 電感電壓 ； 電荷 ； 動態時序分析器

並列摘要

Due to the effect of IR-drop and Ldi/dt, power supply noise can cause yield loss when testing VLSI chips. In this thesis, we propose a power-supply-noise-aware dynamic timing analyzer, IDEA (IR-Drop-aware Efficient timing Analyzer). The proposed analyzer provides reasonable accuracy at much faster speed than existing tools. This technique is very scalable because it is based on linear functions, instead of solving nonlinear functions. The experimental results show, for small circuits, the error is less than 1% compared with HSPICE. For large circuits, we achieved eight times speed up compared with NANOSIM. IDEA identifies 369 timing-violation test patterns (out of 31K test patterns) for a 1M gate benchmark circuit which are difficult to detect by traditional techniques.

並列關鍵字

power supply noise ； IR-drop ； Ldi/dt ； charge ； dynamic timing analyzer

參考文獻

[Aparicio 2012] M. Aparicio, M. Comte, F. Azais, Y. Bertrand, M. Renovell, J. Jiang, I. Polian and B. Becker, “An IR-Drop Simulation Principle Oriented to Delay Testing,” 27th Conference on Design of Circuits and Integrated Systems (DCIS), Avignon, France, 2012.

[Jiang 2013] J. Jiang, M. Aparicio, M. Comte, F. Aza‥ıs, M. Renovell and I. Polian, “MIRID: Mixed-Mode IR-Drop Induced Delay Simulator,” Proc. of Asian Test Symposium, Nov. 2013, pp. 177-182.

[Ahmadi 2003] T. Ahmadi and F. Najm, “Timing Analysis in Presence of Power Supply Noise and Ground Voltage Variations,” Proc. IEEE Int. Conf. Comput.-Aided Design, 2003, pp. 1–8.

[Ahmed 2007] N. Ahmed, M. Tehranipoor, and V. Jayaram, “Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design,” Proc. of Design Automation Conf., 2007, pp. 533-538.

[Aparicio 2013] M. Aparicio, M. Comte, F. Azais, M. Renovell, J. Jiang, I. Polian, B. Becker, “Pre-characterization Procedure for a Mixed Mode Simulation of IR-Drop Induced Delays,” Proc. of IEEE LATW, 2013.