基於協定抽象化技術來進行暫存器至事件轉移階層之建模方法

RTL-to-TL Model Generation Based on Protocol Abstraction Techniques

鄭嘉勳(Chia-Hsun Cheng)

指導教授 ： 黃鐘揚

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2014年)

https://doi.org/10.6342/NTU.2014.01993

摘要

模擬驗證方法是數位電路設計中的基本驗證方法。從簡單的控制器到複雜的系統晶片，設計日趨複雜。複雜度的提升使得傳統的暫存器轉移階層模擬益形緩慢，不能滿足以多個模組所構成之系統晶片在系統層級模擬的速度要求。
這個研究致力於提升模擬速度的方法，提出一個從既有暫存器轉移階層設計產生事件轉移階層的SystemC模型的建模方法，SystemC是電子系統設計的開放業界標準。
從暫存器轉移階層到事件轉移階層，時間的顆粒度是不同的，兩個模型的等價性必須被重新定義以跨越不同的抽象階層。要達成抽象化但是同時保留相當程度的等價性，我們定義了協定規格語言，讓使用者去描述暫存器轉移階層中的協定信號交換和事件邊界。從暫存器轉移階層設計和協定規格，我們使用正規方法與編譯器轉換技術去抽取與簡化正規模型 - 擴充式有限狀態機。在最後的程式碼產生階段，最佳化與產生對應的事件轉移階層SystemC模型。
實驗結果顯示，模擬速度可以達到數倍的加速，同時也免於手動去產生正確的無時序性SystemC模型所需的人力資源。

關鍵字

SystemC ； 事件轉移階層模型 ； 虛擬模擬平台 ； 協定規格語言 ； 擴充式有限狀態機 ； 二元決定圖 ； 編譯器轉換技術

並列摘要

Simulation-based verification is a fundamental verification methodology for validating digital designs. The ever-increasing complexity of system arises from design growing from simple controllers to complex System-on-Chips (SoCs).
The complexity leads to the slow simulation-speed for system-level Register Transfer Level (RTL) simulation that cannot catch up with the growing complexity of integrated RTL blocks on a SOC. This work proposes the techniques to increase the simulation speed by transforming the designs from RTL to transaction-level (TL) models in SystemC, a standard for modeling electrical systems.
From RTL to TL, the timing granularity is different and the notion of equivalence should be redefined to cross different abstraction levels. To achieve the abstraction and maintain the equivalence, we defined the Protocol Specification Language (PSL) for user to formulate the handshaking signals and cared transaction boundaries in RTL. From the RTL description and PSL specification, the formal model – Extended Finite State Machine (EFSM) can be extracted and simplified based on formal and compiler transformation techniques. In the last code generation phase, we perform several optimizations and generate corresponding TL SystemC simulation models.
The experimental results show that the simulation speed can be increased several times and the manual effort to craft the correct untimed SystemC model can be alleviated.

並列關鍵字

SystemC ； Transaction Level Modeling ； virtual platform ； Protocol Specification Language ； Extended Finite State Machine ； Binary Decision Diagram ； compiler transformation techniques

參考文獻

[1] IEEE Standard for Standard SystemC Language Reference Manual, IEEE Standard 1666, 2011.

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