應用於晶片間的12Gb/s電容耦合接收器

隨著製程的演進，晶片內部的時脈也越來越快。相對地晶片與晶片間的傳輸速度卻進步緩慢。因此，設計出一個高速的晶片與晶片間的收發器變成一個重要的課題。本論文提出了一個高速且低功率損耗應用於晶片間傳輸的電容耦合式接收器，裡面包含了一個耦合電容，偏壓電路，低擺幅脈衝轉換器，一個限制放大器，以及一個輸出緩衝器。在此種電路架構裡面，信號是以脈衝波的型式在傳輸線中傳送，透過電容值的選取，可以有效的控制脈衝波的振幅和長度，以降低ISI。脈衝波經由偏壓電路，可以適當的選取直流準位，使得下一級電路的電晶體可以操作在正確的區域。脈衝波經由傳輸線傳遞後再由脈衝轉換器解回NRZ信號，同時此脈衝轉換器也具有低頻補償的功用。限制放大器使用主動電感技巧，它的功能則是可以提升頻寬。為了將解回的訊號送出至晶片外，以便我們可以在示波器觀察，最後透過一個輸出緩衝器，來將訊號推出。放大從前級出來的信號，送至輸出端。經由模擬以及量測結果，此接收器可操作在12Gb/s，符合HDMI1.4a 的規格 (10.2Gb/s)，此時的消耗功率為19.3mW，為一個高速低功耗的接收器。此電路是用TSMC 0.18μm CMOS 製程來驗證此電路架構，晶片面積為850×700um^2 。使用PRBS給資料，將資料經由10 公分的FR4 傳輸線來傳輸，量測結果顯示此接收器的最高工作速度可以操作在12Gb/s。

關鍵字

電容耦合；晶片與晶片間傳輸；主動電感；低面積；接收器

並列摘要

As technology scaling, the frequency of on-chip circuits are much faster, however the speed of off-chip structures are slower. Designing high-speed, lower power and high-density I/O become very important to fill the gap between on-chip and off-chip bandwidth and other problems. Some papers proposed AC coupled interconnect (ACCI) to solve above problem. This thesis proposed an AC coupled chip-to-chip receiver for high density interconnect. The receiver includes capacitive coupling capacitors, bias circuit, pulse converter, limited amplifier and output buffer. The function of the pulse converter convert a return zero (RZ) pulse into non-return zero (NRZ) data from the transmitted side. The amplitude of the receiver is still small, we design a limiting amplifier to amply. Active peaking technique is applied to enhance the bandwidth of the limited amplifier which is occupied smaller area than on-chip spiral inductor. In conclusion, the proposed receiver can operate at 12 Gb/s and the power consumption is 19.3 mW with 135-fF on-chip coupling capacitors, which achieves the specification of HDMI1.4a (10.2Gb/s). The chip is fabricated with TSMC 018μm COMS process It also occupies an active area of 0.0512mm^2.

並列關鍵字

ACCI ； active peaking ； small area ； high speed ； receiver

參考文獻

[1] S. Mick, J. Wilson, and P. Franzon,” 4 Gbps high-density AC coupled interconnection,” in IEEE Custom Integr. Circuits Conf., May 2002, pp. 133-140.

[2] Lei Luo, John M. Wilson, Stephen E. Mick, Jian Xu, Liang Zhang, and Paul D. Franzon, “3Gb/s AC Coupled Chip-to-Chip Communication Using a Low Swing Pulse Receiver”, IEEE JSSCC, VOL. 41, NO. 1, 2006

[3] T. Gabara and W. Fischer, “Capacitive coupling and quantized feedback applied to conventional CMOS technology,” IEEE J. Solid-State Circuits, vol. 32, no. 3, pp. 419–427, Mar. 1997.

[4] J. Kim, I. Verbauwhede, and M.-C. F. Chang, “A 5.6-mW 1-Gb/s/pair pulsed signaling transceiver for a fully AC coupled bus,” IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 1331–1340, Jun. 2005.

[5] S. E. Mick, J. M. Wilson, and P. D. Franzon, “4 Gbps high-density AC coupled interconnection,” in Proc. IEEE Custom Integr. Circuits Conf, pp. 133–140, May 2002.

國際替代計量

應用於晶片間的12Gb/s電容耦合接收器

全文下載

主題瀏覽