使用次諧波電流注入鎖定的多頻帶共存突發式時脈資料回復電路

隨著現代的資訊流通量不斷地成長，被動式光纖網路也被廣泛地鋪設並投入商品化的應用中。在被動式光纖網路的系統裡，上行的資料是採用突發式的傳輸方式，也因此在上行資料的接收器內，會需要一個可以快速回復資料的突發式時脈資料回復電路。　　目前最新一代制定的被動式光纖網路標準為IEEE 802.3av，依據此標準的規範，在該網路中所上傳的串流內可能會有1.25 Gb/s跟10 Gb/s這兩種不同資料傳輸率的突發式資料封包共存，而且在任兩個相鄰封包之間只會有一段極短的時間間隔，因此無法採用傳統方法在此時間內調整振盪器的頻率，來還原不同速率的資料。因此本論文提出了一個使用次諧波電流注入鎖定技巧的突發式時脈資料回復電路，在此架構內，只要振盪器頻率能維持在資料傳輸率的某個正整數倍數上，則即使不重新調整振盪器頻率，也依然可以達到快速回復不同資料傳輸率的資料的功能。　　此外，由於在現有的文獻中，對於使用電流注入鎖定的突發式時脈資料回復電路的分析並沒有詳細地著墨，而為了使電路設計的流程可以跟被動式光纖網路的規範更緊密結合，所以這類突發式時脈資料回復電路的分析也是這份研究論文的主題。　　此電路的規範是參考IEEE 802.3av的標準來加以延伸，並以設計一個可以支援10, 5, 2.5, 1.25 Gb/s等四個頻帶共存的突發式時脈資料回復電路為目標。這個電路使用台積電65奈米CMOS製程來設計，核心面積為0.15 x 0.15 mm2，在1伏特的電壓供應下的功耗為27 mW，量測結果可以達到5、2.5、1.25這三個頻帶共存，鎖定時間跟位元誤碼率皆可達到1 bit跟10 -12，可容忍連續相同二元值長度各自可達到32、16、7 bits，峰對峰抖動則各為104、62.2、35.6 ps。

關鍵字

時脈資料回復電路；突發式；被動式光纖網路；電流注入鎖定；數位控制振盪器；連續相同二元值

並列摘要

In recent years, as the communication traffic constantly grows, the passive optical network (PON) systems become extensively deployed to fulfill the enormous requirements of broadband network. In the PON systems, the upstream data is transmitted in burst-mode, thus a burst-mode clock and data recovery (CDR) circuit which can acquire fast data recovery function is required in the upstream receiver end. In the latest PON standard, IEEE 802.3av, there are 10 and 1.25 Gb/s data packets coexisting in upstream. Between any two adjacent data packets, a very short period of guard time separates them. Although a conventional CDR can adjust its oscillator frequency to deal with the data-rate change; however, this guard time is too short for a CDR to adjust frequency in time. Thus, a conventional burst-mode CDR may not support the coexistence feature. In this thesis, a burst-mode CDR circuit applying sub-harmonic injection-locking technique is proposed. By this technique, the input data at different rates can still be recovered correctly without frequency adjustment if the oscillator frequency is around an integer multiple of the data-rate. Besides, the analysis of burst-mode CDRs basing on injection-locking technique is not focused in previous works. In order to relate the circuit design flow to the PON specifications more tightly, the analysis of this type of burst-mode CDR also plays an important role in this thesis. The circuit specification is mainly referred to IEEE 802.3av standard, and the objective is to design a burst-mode CDR which can support 10, 5, 2.5, 1.25 Gb/s data-bands coexistence. This work is implemented in TSMC 65 nm CMOS technology, and the core area is 0.15 x 0.15 mm2. Moreover, this circuit consumes 27 mW from 1 V supply voltage. From measurement results, the coexistence of 5, 2.5, and 1.25 Gb/s is achievable. Locking times and bit error rates at these three bands are all 1 bit and 10 -12, respectively. The tolerable consecutive identical digits (CID) lengths are longer than 32, 16, and 7 bits, respectively. The peak-to-peak jitters are 104, 62.2, and 35.6 ps, respectively.

並列關鍵字

clock and data recovery circuit ； burst-mode ； passive optical network ； injection-lock ； digital-controlled oscillator ； consecutive identical digits

參考文獻

[11] L. C. Cho, C. Lee, C. C. Hung, and S. I. Liu, “A 33.6-to-33.8 Gb/s Burst-Mode CDR in 90 nm CMOS Technology,” IEEE Journal of Solid-State Circuits, vol. 44, no. 3, pp. 775-783, March 2009.

[2] Y. Ohtomo et al., “High-Speed Circuit Technology for 10 Gb/s Optical Burst-Mode Transmission,” Optical Society of America, NFOEC, March 2010.

[5] B. Razavi, Design of Integrated Circuits for Optical Communications, New York: McGraw-Hill, 2003.

[6] H. Katsurai, H. Kamitsuna, H. Koizumi, J. Terada, Y. Ohtomo, and T. Shibata, “An Injection-Controlled 10-Gb/s Burst-Mode CDR Circuit for a 1G/10G PON System,” IEICE Transactions on Electronics, vol. E94.C, pp. 582-588, Jan. 2011.

[7] C. Melange et al., “Mixed Analogue / Digital Phase Picking Algorithm in Oversampling Burst-Mode Clock Phase Alignment,” Electronics Letters, vol. 45, no. 13, June 2009.

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使用次諧波電流注入鎖定的多頻帶共存突發式時脈資料回復電路

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