滿足多樣測試需求之具確定性平行化自動測試圖樣產生技術

Deterministic Parallel ATPG Techniques to Meet Diverse Test Generation Requirements

葉琨煒(Kuen-Wei Yeh)

指導教授 ： 黃俊郎

國立臺灣大學/電機資訊學院/電子工程學研究所/博士(2017年)

https://doi.org/10.6342/NTU201700829

摘要

自動測試圖樣產生技術被廣泛運用於對測試電路產生測試圖樣。雖然自動測試圖樣產生技術的複雜度能在掃瞄鏈模式下降低，日漸增大的電路規模及複雜的錯誤模型使得自動測試圖樣產生技術越來越耗時。多核心及多電腦平行處理是目前加速自動測試圖樣產生技術的熱門作法。然而，平行化自動測試圖樣產生技術也帶來新的挑戰及問題，例如測試圖樣數量膨脹及測試圖樣產生結果不確定性。到目前為止，所提出的平行化圖樣產生技術皆無法完全解決這些副作用。
本論文提出多個具確定性且同時考慮規模性加速及測試圖樣品質之平行化圖樣產生技術。首先，我們提出一個能達到規模性加速並降低測試圖樣數量膨脹的技術。接著，我們提出一個能完全消除測試圖樣數量膨脹及提升測試圖樣效率的流程。最後，為了同時將規模性加速及測試圖樣品質納入考量，我們提出混合式平行化圖樣產生技術，能同時達到規模性加速並同時提升測試圖樣效率及增加錯誤涵蓋率。

關鍵字

自動化測試圖樣產生技術 ； 平行自動化測試圖樣產生技術 ； 規模性加速 ； 測試圖樣品質 ； 確定性

並列摘要

Automatic test pattern generation (ATPG) is widely utilized to generate test patterns for circuit under test (CUT). Although the complexity of ATPG has been reduced under scan chain testing, increasing circuit size and more complex fault model makes ATPG more time-consuming. Multi-CPUs and multi-computers parallel techniques are the most popular ways to speed up ATPG. However, the parallelized ATPGs also brought new challenge and problems, such as test pattern inflation and non-determinism. As so far, there’s no previous work to fully solve these side effects.
This thesis proposes three deterministic parallel ATPG techniques to consider determinism, scalable speedup, and test quality. This dissertation starts with a new technique, which aims at achieve scalable speedup and reduces test pattern inflation. Next, we proposed an effective flow to fully eliminate test pattern inflation and enhance pattern effectiveness. Finally, to take both scalable speedup and test quality into consideration, we proposed a hybrid parallel ATPG approach which achieves scalable speedup but also enhances the fault coverage and pattern effectiveness.

並列關鍵字

ATPG ； Parallel ATPG ； Scalable speedup ； Test quality ； Determinism

參考文獻

[1]K.-W. Yeh, J.-L. Huang, H.-J. Chao, and L.-T. Wang, “A circular pipeline processing based deterministic parallel test pattern generator,” in Proc. IEEE Int. Test Conf., Sept. 2013, pp. 1–8.

[2] X. Cai, P. Wohl, and D.Martin, “Fault sharing in a copy-on-write based atpg system,” in Proc. IEEE Int. Test Conf., Oct. 2014, pp. 1–8.

[3] X. Cai and P. Wohl, “A distributed-multicore hybrid atpg system,” in

[4] X. Cai, P. Wohl, J. Waicukausi, and P. Notiyath, “Highly efficient parallel ATPG based on shared memory,” in Proc. IEEE Int. Test Conf., Nov.2010, pp. 1–7.

[5] Chun-Hao Chang, K.-W. Yeh, Jiun-Lang Huang, and Laung-Terng Wang, “Sdc-tpg: A deterministic zero-inflation parallel test pattern generator,” in Proc. IEEE Int. Asian Test Symp., Nov.2015, pp. 43–48.