頻率相依晶片電感之模塑

晶片電感的模塑是現今超大型積體電路設計中最熱門的話題之一。快速且準確地根據不同的操作頻率計算晶片電感的值是很重要的。隨著操作頻率超過十億赫茲，晶片電感所造成的效應將不能再像往常一樣的被忽略。有許多不同的研究專注在模塑晶片電感的效應，而他們大部分都是場擷取器(field solver)，例如FastHenry。場擷取器提供了精確的量測以及模擬結果，但是他們卻需要花費很多算上的時間。在這篇論文裡，我們提出了一個新的方法來模塑晶片電感，而這個方法是針對集膚效應(skin effect)這個現象為主。我們首先套用容積細絲模型(volume filament model)來將導線本身切成更小的細絲(filament)，然後測量每一條的電感值。在這之後，我們我們會將每一條測出來的值，乘以一個由電流分布密度(current density distribution)得來的衡量因子(weighting factor)。在這裡，我們為了將電流分布密度的預測簡單化，我們會使用數學近似的方法。當最後每條細絲都乘上了衡量因子，我們會把他們加總，得到最後的電感值。由於使用了近似的公式來預測電流分布密度，我們可以大大的減少自身電感(self inductance)以及相互電感(mutual inductance)的測量上所需要的計算時間，而且不會損失其準確性。因此，整個晶片上的晶片電感萃取便可快速且準確地被完成。

關鍵字

電感；集膚效應

並列摘要

On-chip inductance modeling is one of the most popular issues in VLSI designs nowadays. It is important to calculate on-chip inductance values efficiently and accurately according to the operating frequencies. As the operating frequency reaches over gigahertz, the effect of inductance can no longer be ignored as it used to be. There are many of different researches focusing on modeling on-chip inductance and most of them are field solvers such as FastHenry. Field solvers provide accurate evaluated results but they require much more computational complexity and are time consuming. In this Thesis, we proposed a new method of modeling on-chip inductance that features the skin effect phenomenon. We first apply the volume filament model to divide the traces into smaller filaments and then evaluate the inductance value of each filament. After that, we multiply each filament with a weighting factor, which is derived from the current density distribution in the trace. Here we made the prediction of current density distribution easy to calculate by using mathematical approximation. Having all the weighted inductance value of each filament, we can therefore derive the inductance value of the whole trace. By using the approximated formulation of current density distribution, we can tremendously decrease the time of evaluating both self-inductance and mutual inductance values without losing accuracy. Therefore, the whole chip inductance extraction can be completed accurately and efficiently.

並列關鍵字

inductance ； modeling ； skin effect

參考文獻

[12] L. He, N. Chang, S. Lin, and O. S. Nakagawa, “An Efficient Inductance Modeling for On-Chip Interconnects,” Custom Integrated Circuits Conference, pp. 457-460, May 1999.

[18] Raphael User Manual, Avant! Corporation.

[1] F. W. Grover, Inductance Calculations: Working Formulas and Tables, Dover Publications, 1973.

[2] S. H. Hall, G. W. Hall, and J. A. McCall, High-Speed Digital System Design, John Wiley & Sons, Inc., 2000.

[3] M. Kamon, M. J. Tsuk, and J. K. White, “FastHenry: a Multipole Accelerated 3-D Inductance Extraction Program,” Design Automation Conference, pp. 678-683, Jun. 1993.

國際替代計量

頻率相依晶片電感之模塑

全文下載

主題瀏覽