透過您的圖書館登入
IP:3.17.162.247
  • 學位論文

二硫化鉬及二硫化鎢傳輸特性及其電晶體之研究

Studies of Materials and Transport Properties of MoS2 and WS2 Based Transistors

指導教授 : 吳育任

摘要


本研究以蒙地卡羅法討論二硫化鉬以及二硫化鎢的傳輸特性,經模擬後得知二硫 化鉬及二硫化鎢的電子遷移率分別為171 cm2/V-s 及83 cm2/V-s。此外,能帶中,K 能谷以及Q 能谷間的能量差是影響材料傳輸特性的重要因素。但若將二維材料周圍以高介電係數材料包覆,遠程聲子散射將會成為最重要降低材料速度的因子。我們將討論完的材料特性帶入二維奈米片電晶體討論元件特性。材料、閘極長度、電極交疊區域、介電層以及電子摻雜將被討論。我們發現相較於二硫化鎢,二硫化鉬會是較好的通道材料。至於介電層,因三氧化二鋁較二氧化鉿有較低的遠程聲子散射,會是較好的介電層材料。電極交疊區域縮短以及摻雜能給電流帶來正面的效應。至於閘極長度的選擇,則要在縮短閘極的好處以及閘極控制力下降間來選擇。在眾多的參數間進行優化後,我們設計出一電晶體,其閘極長度七奈米,電極交疊區域一奈米,介電層為等效氧化層厚度0.8 奈米之氧化鋁以及電子摻雜為4×1013 cm-2。此電晶體在操作電壓0.65伏以及截止電流為1×10-4 μA/μm 下,開路電流可達495 μA/μm,符合國際半導體技術發展藍圖於2022 年對電流之要求。此外,其亦展現出良好的閘極控制能力。

並列摘要


Transport properties of MoS2 and WS2 are investigated by the Monte Carlo method. Intrinsic mobilities of MoS2 and WS2 are 171 cm2/V-s and 83 cm2/V-s . Besides, for the free-standing MoS2 and WS2, the valley energy separation between the K and Q valley is the critical factor influencing transport. However, if 2D materials are stacked in high-κ materials, remote phonon scattering becomes the most important scattering mechanism and degrades the performance of the material very much. In addition, 2D nanosheet transistors are discussed. Effects of the materials, the gate length (LG), the length of the underlap region (Lun), dielectrics, and doping are studied. We found out MoS2 is more suitable for the channel material. As for the dielectric, Al2O3 is better than HfO2 due to the weak remote phonon scattering. Lun and doping can bring positive effects on on-current (Ion). The selection of LG is a trade-off between shrinking and gate control. After optimization, maximum Ion happens at LG=7nm, Lun=1nm, 0.8nm EOT of Al2O3 dielectric and n-type doping of 4×1013 cm−2. Ion can reach 495 µA/µm when the supply voltage is 0.65V and off-current is ×10−4 µA/µm, meeting the requirement of 2022 International Roadmap for Devices and Systems. Furthermore, it also demonstrates good gate control and electrostatics.

參考文獻


L. Yang, K. Majumdar, Y. Du, H. Liu, H. Wu, M. Hatzistergos, P. Hung, R. Tieckelmann, W. Tsai, C. Hobbs et al., “High-performance MoS 2 fieldeffect transistors enabled by chloride doping: Record low contact resistance (0.5 ku μm) and record high drain current (460 μA/μm),” in 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers. IEEE, 2014, pp. 1–2. vii, 9
M.-C. Chen, K.-S. Li, L.-J. Li, A.-Y. Lu, M.-Y. Li, Y.-H. Chang, C.-H. Lin, Y.-J. Chen, Y.-F. Hou, C.-C. Chen et al., “TMD FinFET with 4 nm thin body and back gate control for future low power technology,” in 2015 IEEE International Electron Devices Meeting (IEDM). IEEE, 2015, pp. 32–2. vii, 9
A. Nourbakhsh, A. Zubair, A. Tavakkoli, R. Sajjad, X. Ling, M. Dresselhaus, J. Kong, K. Berggren, D. Antoniadis, and T. Palacios, “Serially connected monolayer MoS 2 FETs with channel patterned by a 7.5 nm resolution directed self-assembly lithography,” in 2016 IEEE Symposium on VLSI Technology. IEEE, 2016, pp. 1–2. vii, 9
S. Park and D. Akinwande, “First demonstration of high performance 2D monolayer transistors on paper substrates,” in 2017 IEEE International Electron Devices Meeting (IEDM). IEEE, 2017, pp. 5–2. vii, 4, 9
C. Huyghebaert, T. Schram, Q. Smets, T. K. Agarwal, D. Verreck, S. Brems, A. Phommahaxay, D. Chiappe, S. El Kazzi, C. L. De La Rosa et al., “2D materials: roadmap to CMOS integration,” in 2018 IEEE International Electron Devices Meeting (IEDM). IEEE, 2018, pp. 22–1. vii, 9

延伸閱讀