應用於24GHz頻率合成器之多模除數除頻器

A Multi-Modulus Divider For 24 GHz Frequency Synthesizer

林盈達(Yin-Ta Lin)

指導教授 ： 黃天偉

國立臺灣大學/電機資訊學院/電信工程學研究所/碩士(2010年)

https://doi.org/10.6342/NTU.2010.02621

摘要

以鎖相迴路為基礎的頻率合成器被大量使用在近代的通訊系統當中。多模除數除頻器是頻率合成器中，相當重要的一個設計元件。一個穩定參考頻率經由除數的變換，可得到想要的輸出頻率。
本論文是利用0.18微米CMOS製程來設計與實現多模除數除頻器。多模除數除頻器分三階段實行，實作概要如下:
第一個電路是一個串聯多級D型正反器的除頻器，藉由此電路對於電流模式邏輯閘與TSPC電路的設計有更進一步了解。
第二個電路是一個雙模除數除頻器。雙模除數除頻器通常關係到整個除頻器的操作頻率，此電路藉由D型正反器與NAND閘的結合來減少路徑上的傳播延遲。
第三個電路是一個除數64到67的除頻器，一般多模除數除頻器的組成分三部份，除4/5雙模除頻器，同步計數除頻器與數位控制的部分。雙模除頻器先操作在較高的頻率，再將低頻訊號輸入同步計數除頻器。
根據量測的結果，不同的除數模數都可藉由改變數位控制量測到。此電路將來也可應用於頻率合成器的實踐當中。

關鍵字

頻率合成器 ； 多模除數除頻器 ； 雙模除數除頻器

並列摘要

PLL-based frequency synthesizers have been used widely in modern communication systems. The multi-modulus divider is one of the key elements in the frequency synthesizer. The desired output frequency could be derived from stable reference frequency by selecting different modulus.
This thesis presents the design and implemented of multi-modulus divider. The chips have been implemented and fabricated in 0.18μm CMOS technology. The implement of multi-modulus divider could be accomplished in three steps.
The first chip is a divider chain consists of CML and TSPC flip-flop based dividers. More design details about static divider could be learned from this chip.
The second chip is a divide-by-4/5 prescaler. Prescaler usually dominates the speed of the whole divider. A modified D flip-flop merged with NAND gate function is used in this prescaler to reduce the propagation delay.
The third chip is the whole divide-by-64~67 divider. The frequency divider is composed of three parts – a divide-by-4/5 prescaler, an asynchronous divide-by-2N counter and digital control block. The high-speed prescaler operates at high frequency, feeding the lower frequency to the low-speed counter.
The measurement results indicate that there are four division ratios could be selected. The circuit is fit for the implemented of frequency synthesizer.

並列關鍵字

Frequency Synthesizer ； Prescaler ； Frequency Divider

參考文獻

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