0.13 µm CMOS 頻率倍率計算器

全數位鎖相迴路一直是個熱門的主題，因為數位電路的特性，可以快速的替換到不同製程上。而傳統的小數型鎖相迴路運用利用二元式相位偵測器或是時間數位時間轉換器來偵測輸入頻率與參考頻率之間的時間差。而本論文提出頻率倍率計算器來取代原先的二元式相位偵測器和時間數位時間轉換器的功能來達到更快速的鎖定。本論文提出的頻率倍率計算器，計算輸入訊號與參考頻率之間的倍率，由全數位的方式實現，透過數學的統計運算，能不受製程限制，突破最小時間解析度，單一個反相器的時間延遲，因為統計的特性，可以免去傳統架構設計上達到高解析度需要的複雜校正電路。若不考慮面積和功耗的情況下，根據數學模型推論可以依要求幾乎無限制的提高時間解析度直到應用所需要的量級。在使用0.13微米CMOS製程實現的頻率倍率計算器，晶片面積為0.96 × 0.7 mm2，實際電路面積為 0.375 × 0.145 mm2，根據量測結果，在1.2 V供應電壓下，使用平行化的128組時間延遲單位以及7組參考頻率周期的狀況下，量測的頻率範圍在135-850 MHz之間，其算出的倍率準確度可以在小數點後兩位以內，並且鎖定時間只需要兩個參考頻率的時間。

關鍵字

時間數位轉換器；全數位頻率合成器；頻率倍率計算器；快速鎖定

並列摘要

Digital PLLs have become popular because of easy adaptation to different CMOS technology. The conventional approach of developing fractional-N PLLs utilizes bang-bang phase frequency detector (BBPFD) and time-to-digital converter (TDC) to detect the timing difference between the scaled signal and reference clock. This thesis presents the first frequency ratio calculator (FRC) as an alternative function block to BBPFDs and TDCs in digital PLLs for fast locking. In this thesis, a technique of Frequency Ratio Calculator (FRC) is proposed. The FRC gives out both the integer and fraction of the frequency ratio between an input signal and a reference clock by statistical means. Based on derived statistic model and system architecture, high resolution of the converter is achieved. The minimum resolution will not restrict by the minimum gate delay of inverter chain available in a process technology. Also, due to intrinsic statistical property, the FRC reveals fully insensitive characteristics against device/process variation of fabrication technology. Therefore, design complexity of calibration circuit required in tradition design can be avoided. According to derived mathematical model, the minimum resolution of proposed FRC can achieve almost unlimited order of magnitude, without considering area and power consumption. The FRC is implemented in 0.13 um CMOS technology. The chip size is 0.96 × 0.7 mm2, and the core size is 0.375 × 0.145 mm2. The FRC was tested under a supply voltage of 1.2V. In the frequency range between 135 MHz and 850 MHz, the measured ration accuracy is smaller than 0.01 and the calculation time only takes up two periods of reference clock.

並列關鍵字

TDC ； ADPLL ； FRC ； Fast Locking Technique

參考文獻

[1] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001.

[3] R. D. Yates and D. J. Goodman, Probability and Stochastic Processes, John Wiley & Sons, 2005.

[6] Z. Cheng, X. Zheng, M. J. Deen, H. Peng, “Recent developments and design challenges of high-performance ring oscillator CMOS time-to-digital converters,” IEEE Trans. Electron Devices, vol. 63, no. 1, pp. 235-251, Jan. 2016.

[7] P. Dudek, S. Szczepanski, and J. V. Hatfield, “A high-resolution CMOS time-to-digital converter utilizing a vernier delay line,” IEEE J. Solid-State Circuits, vol. 35, no. 2, pp. 240-247, Feb. 2000.

[8] E. Temporiti, C. Weltin-Wu, D. Baldi, R. Tonietto, and F. Svelto, “A 3 GHz fractional all-digital PLL with a 1.8 MHz bandwidth implementing spur reduction techniques,” IEEE J. Solid-State Circuits, vol. 44, no. 3, pp. 824-834, Mar. 2009.

國際替代計量

0.13 µm CMOS 頻率倍率計算器

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