應用於IEEE802.11正交分頻多工調變系統之低複雜度無乘法器快速傅立葉轉換器之設計及分析

在本篇論文中，提出一個適用於IEEE 802.11a 及 802.11n 無線區域網路系統之無乘法器快速傅力葉轉換器以及其固定點錯誤分析方法。此快速傅立葉轉換器是基於radix-2/4/8演算法，並藉由位移及相加操作概念使twiddle因子複數乘法器實現無乘法器操作。甚者，利用系統兩倍頻的昇頻特性，將提出的複數乘法器中之量值部分再減少一半的硬體。處理單元方面也做出改善，同樣利用系統兩倍昇頻特性將其中一個加法器換成一個多工器及一個反轉器。並比較三種常見之儲存單元，SRAM，DFF，暫存器檔案，找出面積及功率損耗最佳化之儲存器類型。此外，如計數器之共用，位元倒置址產生方式以及反傅立葉轉換/傅立葉轉換之切換等傅立葉轉換器其他考量均有論述。此傅立葉轉換器在節省硬體成本下，仍可達到兩系統需求之40MHz操作頻率下38.36dB量噪訊比及25.79dB噪訊比的表現。而所提出的錯誤分析方法是專門用在radix-2/4/8演算法，其基於建立數個蝴蝶單元的雜訊模型，並將雜訊來源分為常數乘法，旋轉因子複數乘法以及處理單元之輸入輸出量化產生的雜訊三種。經模擬驗證後，可由量化字元長度及旋轉因子係數之量噪訊比來估算對應到系統需求噪訊比之快速傅立葉轉換器輸出之總雜訊大小，進而節省模擬成本。換句話說，對於給予的系統需求噪訊比，也可反推出快速傅立葉轉換器之各個係數。而提出的快速傅立葉轉換器硬體節省方法及錯誤分析方法均可適用在更大之延伸點數的快速傅立葉轉換器上。此外，由C建立802.11a OFDM及802.11n MIMO-OFDM的基頻系統之模擬環境。OFDM系統包括符元邊界偵測，通道估算，可適性頻域等化以及載波頻率偏移等同步。MIMO-OFDM系統則是有符元邊界估測，通道估算和MIMO解碼。快速傅立葉轉換器建立此兩系統上，由C作浮點數及定點數模擬，再根據硬體化的定點模擬撰寫Verilog RTL程式。此外，經由QuatusII做合成以及電路的放置及繞線，然後將此快速傅立葉轉換器由Altera Stratix EP1S80 DSP板操作在40MHz下實現，總共使用約2600個邏輯單元。最後，使用Tetronix TLA 715的樣本產生器及邏輯分析儀進行量測。

關鍵字

快速傅立葉轉換；正交分頻多工；無乘法器

並列摘要

A cost-e cient multiplierless IFFT/FFT processor and its xed-point error analysis are proposed for IEEE 802.11a and 802.11n WLAN systems. The architecture of IFFT/FFT processor is SDF with radix-2/4/8 algorithm. The multiplicationless operation of the complex twiddle factor is realized by the signed-digit technique. In addition, the nonzero bits of the signed-digit for the complex twiddle factor are optimized to minimize the number of shift-and-add operations to achieve the cost-e cient property. Moreover, in order to optimize the area and power consumption for the storage elements, there are three storage types, SRAM, register file and D-flipflop are discussed and compared. Finally, IFFT/FFT processor is designed to satisfy the system specification with the SNR=26dB and SQNR=38dB. Furthermore, PER is less than 0.1 based on the system simulation with the xed-point IFFT/FFT processor. The xed-point error analysis of IFFT/FFT processor is presented for SDF architecture with radix-2/4/8 algorithm. The xed-point error is composed of three quantization error sources, nonideal W factor, nonideal twiddle factor coe cient and the truncation error. Based on the xed-point analysis, the total noise power of FFT output can be derived in terms of the three error sources. Signi cantly, the lower bound of IFFT/FFT processor parameters could be determined by the system required SNR. Finally, the MSE between the proposed analysis and the simulation result is less than 1%. The proposed cost e cient FFT and error analysis can also be extended to other application systems, such as 802.16, DVB and etc. A C simulation model is developed for IEEE 802.11a (SISO-OFDM) and 802.11n (MIMO-OFDM) WLAN systems respectively. In addition, the hardware-like fixed-point simulation model is exploited to design the Verilog RTL code and used to the systemsimulation. The prototype of the 64-point FFT is evaluated by Altera Stratix EP1S80 DSP development board on 40MHz with approximately 2600 logic elements. Finally, the FFT emulation is measured by Tektronix TLA715 pattern generator and logic analyzer.

並列關鍵字

FFT ； OFDM ； Multiplierless

參考文獻

[13] Wei-Hsiang Tseng, OFDM Baseband Transceiver Architecture Design and Imple-

[12] Simon R. Saunders, Antennas and Propagation for Wireless Communiication Sys-

[20] Yu-Wei Lin, Hsuan-Yu Liu, and Chen-Yi Lee, "A 1-GS/s FFT/IFFT Processor

[1] Jia, L.,Goa,Y.,Isoho,J., and Yenhunen,H., "A new VLSI-orented FFT algorithm

[2] S.He and M.Torkelson, "Designing pipeline FFT processor for

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應用於IEEE802.11正交分頻多工調變系統之低複雜度無乘法器快速傅立葉轉換器之設計及分析

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