使用新型差動切換脈波拴鎖電路之延遲鎖定迴路型式可程式化時脈產生器設計

隨著大型積體電路製程的進步，時脈產生器被廣泛應用於各類型電路系統，例如微處理器系統、記憶體積體電路、有線與無線網路信號傳輸…等等，都需要產生所需頻率的倍頻時脈，藉以做為同步時脈操作，或者混波降頻的之用途。常見的時脈產生器基礎架構設計方式可分為鎖相迴路(Phase-Locked Loop, PLL)與延遲鎖定迴路(Delay-Locked Loop, DLL)。傳統設計多採用前者；但延遲鎖定迴路具有容易設計的特性，因其本身為二階系統穩定度較佳，在迴路濾波器設計上僅需一個電容，面積可以有效縮小。並同時具有低時間抖動特性。本論文提出在典型架構之脈波產生器內增加更多的倍頻數選擇(增加至12種)；設計新型電路如致能短脈波產生器(Enabled Short-Pulse Generator, ESPG)，差動切換脈波拴鎖電路(Differential Toggle-Pulsed Latch, DTPL)來合成所需之高速合成差動輸出時脈。為了增加應用層面，輸出脈波為雙端輸出且不受延遲鎖定迴路的多相位影響。本研究使用CMOS 0.18μm 1P6M製程，在輸入操作頻率為300MHz∼400MHz下，輸出頻率範圍為150MHz∼1.8GHz，整體晶片核心面積為241 μm x 316 μm。

關鍵字

時脈產生器；延遲鎖定迴路；差動切換脈波拴鎖電路

並列摘要

As the progress of the VLSI technologies, clock generator needed to mix a required clock as an operation of the synchronization or the degradation of the frequency, has been widely implemented in many applications of circuit systems, such as Microprocessor, Memory Integrated Chip, wireless communication. The ordinary structure of a clock generator could be classified into two kinds. One is phase-locked loop(PLL)；the other is delay-locked loop(DLL). The former one is usually adopted by conventional designer but DLL is more suggested because of its stability and easily designed architecture. Furthermore, DLL contents better performance of jitter. There are 12 choices of multiplication factors in the scheme we proposed. The newly circuits, such as enabled short-pulse generator(ESPG), differential toggle-pulsed latch(DTPL), are used to combine the multiphase of the DLL and generate the output clock. The output clock, which is fully differential output to increase the level of applications, wouldn’t be affected by the duty cycle of DLL’s multiphase. CMOS 0.18μm process is used in our work. The output frequency of the reference is between 150MHz to 1.8GHz from the input frequency 300MHz to 400MHz. The chip core area is 0.241mm x 0.316mm.

並列關鍵字

Clock Generator ； Delay-Locked Loop ； Differential Toggle-Pulsed Ltach

參考文獻

[1] H.-H Chang, J.-W Lin, C.-Y Yang and S.-I Liu, “A wide-range delay-locked loop with a fixed latency of one clock cycle”, IEEE J. Solid-State Circuits, Vol. 37, pp.1021-1027, Aug. 2002.

[2] H. Notani et al., “A 622-MHz CMOS phase-locked loop with rechargetype

[3] J.-G. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques”, IEEE J. Solid-State Circuits, vol. 31, pp. 1723-1732, Nov. 1996.

[4] S. Kim, K. Lee, Y. Moon, D.-K. Jeong, Y. Choi, and H.-K. Lim, “A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL”, IEEE J. Solid-State Circuits, vol. 32, pp. 691-700, May 1997.

[5] Hsiang-Hui Chang; Jung-Yu Chang;Chun-Yi Kuo and Shen-Iuan Liu "A 0.7-2-GHz self-calibrated multiphase delay-locked loop" IEEE J. Solid-State Circuits, Vol 41, May 2006

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使用新型差動切換脈波拴鎖電路之延遲鎖定迴路型式可程式化時脈產生器設計

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