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  • 學位論文

60奈米部分解離絕緣體上矽N型金氧半元件二次效應 探討與閘極穿隧電流影響電容分析

Second Order Effect of 60nm PD SOI NMOS and Gate Tunneling Current Related Capacitance Behavior

指導教授 : 郭正邦

摘要


本論文探討部份解離絕緣體上矽N型金氧半(PD SOI NMOS)元件之淺槽隔離對窄通道元件影響,潛槽隔離可能影響電子平均壽命,使得元件特性改變,我們量測不同通道寬度的元件來做比較。接著是討論太薄的閘極氧化層情況下,其閘極漏電流對元件本質電容的影響,模擬閘-源極電容與閘-洩極電容對於不同汲極電壓的變化,並發現部分解離絕緣體上矽N型金氧半元件底部寄生雙載子電晶體導 通時,會引發電流突增現象並且影響元件本質電容,使其產生一突跳現象,接著分析考慮與不考慮閘極漏電流,其考慮閘極漏電流會使電容突跳更加嚴重。第一章介紹絕緣體上矽(SOI)的由來與發展趨勢,接著敘述元件縮小所遭遇的困難,引用ITRS的資料描述現今SOI元件的尺寸與未來趨勢。第二章提出部分解離絕緣體上矽N型金氧半之淺槽隔離對窄通道元件對元件影響,由實驗數據分析並討論。第三章為部份解離絕緣體上矽N型金氧半閘極漏電流對本質電容的影響,透過元件二維模擬器的幫助,可以找出PD SOI NMOS電流突增效應對應本質電容之關 係,與閘極漏電流造成電容的影響。第四章為總結與未來工作。

關鍵字

機械張力 電容

並列摘要


This thesis reports the 2nd order effects of the 65nm PD SOI NMOS device. First, the shallow-trench-isolation-related narrow channel effect on kink effect and the breakdown behavior are analyzed, then the gate tunneling current and the floating-body-effect related capacitance behavior of 65nm PD SOI NMOS device are described. Finally, we make a conclusion and future work.

並列關鍵字

Mechanical capacitance

參考文獻


[3.5]S. S. Chen and J. B. Kuo, “An Analytical CAD Kink Effect Model of
[1.1]P. J. VanDerVoorn and J. P. Krusius, “Inversion Channel Edge in Trench-Isolat ed Sub-1/4-um MOSFET’s,” IEEE Trans. Elec. Dev.,43(8), 1274-1280,1996.
[1.2]H. S. Lee, M. H. Park, Y. G. Shin, T. –S. Park, H. K. Kang, S.I. Lee and M. Y. Lee, “An Optimized Densification of the Filled Oxide for Quarter Micron Shallow Trench Isolation (STI),”VLSI Tech. Dig.,158-159 , 1996.
[1.3]A. Chatterjee, J. Esquivel, S. Nag, I. Ali, D. Rogers, K. Taylor, K. Joyner, M. Mason, D. Mercer, A. Amerasekera, T. Houston and I. C. Chen,“A shallow Trench Isolation Study for 0.25/0.18um CMOS Technologies and Beyond,
[1.5]K. F. Goser, C. Pacha, A. Kanstein, and M. L. Rossmann, “Aspects of Systems and Circuits for Nanoelectronics,“ Proc. Of IEEE, 85(4), 558-576, 1997.

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