With the increasing complexity of designs, verification becomes more and more challenging. Even with formal verification techniques deployed, post-silicon bugs are not uncommon to be found in manufactured chips. For processor designs, post-silicon bugs may possibly be avoided by exploiting software workaround. Although prior work has shown the feasibility, excessive stall operations have to be inserted in the generated assembly code and thus drastically slowing down software execution on a buggy processor. Given a program to be executed on a target buggy processor, in this thesis we propose a QBF-based method to recompile the program into assembly code executable on the buggy processor without triggering bugs while avoiding redundant stall operations. Experimental results show the effectiveness of our proposed method.
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