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  • 學位論文

p型氧化亞銅薄膜之製備和特性探討

Fabrication and Characterization of p-Type Cuprous Oxide Thin Films

指導教授 : 陳奕君

摘要


本論文對各生成條件下之銅系氧化物薄膜進行了結晶相、光學、表面型態和電性分析。除此之外,我們也嘗試利用氧化亞銅製作薄膜電晶體。   在結晶相分析中,隨著濺鍍時氧比例的上升,銅金屬將被氧化而形成氧化亞銅結晶。額外摻入更多的氧則無益於氧化亞銅,過量的氧會阻礙氧化亞銅結晶導致晶粒粒徑的減小,而氧比例過高時則會直接生成氧化銅結晶。當氧化亞銅進行氮氣熱退火時會和氮氣中殘存的氧氣反應生成氧化銅,而進行真空熱退火則在高溫時會傾向析出銅金屬。   在光學分析中,成分呈現氧化亞銅的薄膜具有較高的光學能隙,其值落在2.31-2.42 eV之間。而當薄膜成分中開始出現氧化銅時,其光學能隙將遽降。   在表面型態分析中,未退火的薄膜呈現較為平整的表面。進行熱退火將導致薄膜表面型態的改變,200 °C氮氣和真空退火皆會使薄膜表面產生較明顯的奈米裂痕;退火溫度提升至300 °C以上則薄膜會有顯著的變化,氮氣退火會轉變為氧化銅的結晶型態,而真空退火則會導致銅金屬奈米粒子的析出。   在電性分析上,氧比例1%濺鍍未退火的氧化亞銅薄膜有具有最低的載子濃度和較高的載子遷移率。濺鍍時額外摻入的氧將導致兩種結果,其一為進入氧化亞銅結晶中成為間隙氧,間隙氧成為氧化亞銅中的受體進而使得載子濃度上升;其二是阻礙氧化亞銅結晶,導致氧化亞銅晶粒粒徑的變小和載子遷移率的下降。相對來說,進行200 °C真空退火則有助於結晶性和載子遷移率的提升。薄膜中部分氧化銅的出現將導致載子遷移率的顯著下降。   在下閘極結構之氧化亞銅薄膜電晶體製備中,氧比例1%濺鍍未退火的氧化亞銅薄膜電晶體具有電流開關比~2.1×10^1和場效遷移率1.21×10^-4 cm^2/Vs;氧比例1%濺鍍後經200 °C真空退火之氧化亞銅薄膜電晶體則呈現電流開關比~10^1和較高的場效遷移率1.17×10^-3 cm^2/V s。

關鍵字

p型 氧化亞銅 濺鍍 薄膜電晶體

並列摘要


In this study, we investigated the crystallinity, optical properties, surface morphology and electrical properties of copper oxide films, and used cuprous oxide thin films as the active layers to fabricate thin-film transistors. Copper oxide films were deposited on glass substrates by reactive RF magnetron sputtering. Pure cuprous oxide film can be obtained at an oxygen fraction of 1% during the sputtering. Higher oxygen content leads to the formation of cupric oxide. Thermal annealing was carried out in nitrogen atmosphere and vacuum, respectively. Further oxidation of cuprous oxide film is observed after annealing in nitrogen, which may be attributed to the residue oxygen in the nitrogen. For vacuum annealing, cuprous oxide shows no phase tansition up to 200 °C and metallic copper precipitations are observed at temperature higher than 300 °C. For optical properties, the as-deposited cuprous oxide film deposited at 1% oxygen fraction has the highest optical band gap of 2.42 eV. After vacuum annealing at 200 °C, the band gap reduces to 2.39 eV. The optical tansmittance and band gap of thin films containing cupric oxide phase are significantly reduced. Scanning electron micrographs (SEM) show that annealing has crucial influence on the surface morphology of the cuprous oxide thin films. Nano-scale cracks are observed when the film is annealed at 200 °C in nitrogen and vacuum, which is caused by the release of internal stress inside cuprous oxide thin films after thermal annealing. For vacuum annealing at 300 °C and 400 °C, metallic copper nanoparticles appear on the surface. Hall measurement was carried out to evaluate the electrical properties of the copper oxide films. The as-deposited cuprous oxide film has the lowest carrier concentration of and appropriate carrier mobility of 1.24 cm^2/V s. Addition of excess oxygen during sputtering hinders the crystallization of cuprous oxide and results in a drop of carrier mobility.Vacuum annealing at 200 °C enhances the crystallinity and carrier mobility of the cuprous oxide thin films. At last, staggered bottom-gate top-source/drain thin-film transistors (TFTs) were frabicated using the as-depoisted cuprous oxide film and the 200 °C vacuum annealed one as the channel layers.The as-deposited cuprous oxide TFT exhibits a current on-off ratio of ~2.1×10^1 and a field-effect mobility of 1.21×10^-4 cm2/Vs, while the 200 °C vacuum annealed one shows a current on-off ratio of ~10^1 and a field-effect mobility of 1.17×10^-3 cm^2/V s.

並列關鍵字

p-type cuprous oxide sputtering thin-film transistor

參考文獻


[1] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, "Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors," Nature, vol. 432, pp. 488-492, 2004.
[2] P. F. Carcia, R. S. McLean, and M. H. Reilly, "High-performance ZnO thin-film transistors on gate dielectrics grown by atomic layer deposition," Applied Physics Letters, vol. 88, pp. 123509-1-3, 2006.
[3] Y.-S. Tsai and J.-Z. Chen, "Positive gate-bias temperature stability of RF-sputtered Mg0.05Zn0.95O active-layer thin-film transistors," IEEE Transactions on Electron Devices, vol. 59, pp. 151-158, 2012.
[4] J. S. Park, K. S. Son, T. S. Kim, J. S. Jung, K.-H. Lee, W.-J. Maeng, H.-S. Kim, E. S. Kim, K.-B. Park, J.-B. Seon, J.-Y. Kwon, M. K. Ryu, and S. Lee, "High performance and stability of double-gate Hf-In-Zn-O thin-film transistors under illumination," IEEE Electron Device Letters, vol. 31, pp. 960-962, 2010.
[5] V. Avrutin, D. J. Silversmith, and H. Morkoc, "Doping asymmetry problem in ZnO: current status and outlook," Proceedings of the IEEE, vol. 98, pp. 1269-1280, 2010.

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