缺陷捕捉與照光對具氧化鉿/二氧化矽介電層 金氧半結構電容-電壓特性之影響

Trapping and Illumination Effects on the C-V Characteristics of MOS Structures with HfO2/SiO2 Dielectrics

曾敬凱(Ching-Kai Tseng)

指導教授 ： 胡振國

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2012年)

https://doi.org/10.6342/NTU.2012.03057

摘要

本篇論文為探討在不同製程溫度條件下，超薄氧化鉿高介電常數閘極介電層之電特性。首先在p型矽基板上利用純水陽極氧化技術於室溫生長超薄二氧化矽做為初始緩衝層，並於975℃高溫氮氣中進行快速熱退火，之後再利用濺鍍法在室溫下鍍上鉿薄膜並利用硝酸氧化技術氧化鉿薄膜得到氧化鉿，再配合380℃的高溫爐管，於氮氣中進行熱退火技術10分鐘，可得到等效厚度為2.3nm 的氧化鉿/二氧化矽閘極絕緣層，其等效介電常數為20。與具有相同等效厚度之二氧化矽介電層相比，其閘極漏電流較低100倍。氧化鉿/二氧化矽閘極介電層的電容值隨著頻率的分散現象，在本文將被模擬與詳細討論。在評估氧化鉿和二氧化矽之間界面特性時，利用由高低頻率電容值可求得界面陷阱所導致的電容差值。模擬結果均顯示不同品質之氧化鉿/二氧化矽閘極介電層會造成電容-電壓曲線上不同的頻率分散特性。另外，具氧化鉿/二氧化矽閘極介電層金氧半結構在照光下之電容-電壓以及電流-電壓曲線變化，亦在本文被研究分析。照光下，在空乏區和反轉區電容-電壓曲線將會有隆起變化以及兩個高峰，此現象是由界面陷阱和過剩的載子所造成的。照光下，在反轉區電流-電壓曲線將會達到飽和，而飽和電流與元件周長是成正比的，但在聚集區電流則是與面積成正比。電流飽和之電壓與電容-電壓曲線上電容截止電壓有相關，此截止電壓是與介電層之品質厚薄有關。

關鍵字

金氧半結構 ； 介電層 ； 氧化鉿 ； 電容-電壓曲線

並列摘要

In this work, the electrical properties of high-k gate dielectric (HfO2) prepared under different process temperatures are investigated. Ultra-thin SiO2 layer was prepared by anodization in D. I. water at room temperature for initial buffer layer. The sputtered hafnium films was oxidized by diluted nitric acid (HNO3) followed by 380℃ annealing in N2. The equivalent oxide thickness (EOT) of HfO2/SiO2 gate dielectric is 2.3 nm and the effective dielectric constant is 20. The gate leakage current of this HfO2 gate dielectric is two orders smaller than that of SiO2 dielectric with the same EOT. The frequency dispersion of C-V curves are simulated and discussed in detailed. As for the SiO2 and HfO2 quality, the traps (Ctrap) between SiO2 and HfO2 obtained by high-low-frequency calculation are found. These simulation results show that HfO2/SiO2 with different qualities may introduce different frequency dispersions in C-V curves. Also, the C-V and J-V characteristics of MOS structures with HfO2/SiO2 gate dielectrics are investigated under illumination. The C-V curves are deformed and exhibited two peaks in depletion and inversion regions under illumination, which are caused by Dit and excess carriers. The J-V curves are saturated at inversion region and the saturated current is proportional to the device perimeter. But in accumulation, the current was proportional to the area. The onset voltage of saturation current is corresponding to the cut off voltage, which is dependent on dielectrics quality.

並列關鍵字

High-k ； HfO2 ； dielectric ； MOS ； C-V curve

參考文獻

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Alternating Electric Currents” United Kingdom Patent Office., Patent GB24850.

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