一1.47ps低擾動，120MHz - 1.4GHz寬頻且快速鎖定之全數位延遲鎖相迴路

最近幾年，系統整合的晶片已成為IC設計的趨勢。因此，SoC(System-on-Chip)的設計常常會結合許多知識產權(Intellectual Property)和組件電路，而在這些系統整合的晶片中，延遲鎖相迴路經常被用來同步系統中的時脈。然而，對於越先進的製程而言，類比的延遲鎖相迴路是比較難去實現和設計的，而且容易受到製程、電壓、溫度變化的影響；相反的，全數位的延遲鎖相迴路比較容易實現在高階製程當中，也易與數位系統整合。由於記憶體系統的需求日漸增加，低擾動且寬頻的數位鎖相迴路的需求亦逐漸增多。而全數位鎖相迴路中快速鎖定的特性，在一些有休眠模式的應用中，也是十分重要的指標之一。這份研究的目的即在系統層級中，提出一低擾動，寬頻且快速鎖定之全數位鎖相迴路。此篇論文中提出了一創新電路¬—粗調相位選擇器，來取代傳統數位控制延遲線。粗調相位選擇器不只將頻寬拓寬至120MHz-1.4GHz，並且擁有快速鎖定的特性。在頻寬範圍之內，不論輸入頻率為何，皆只需要7-8個週期便可以完成鎖定。除此之外，使用閉迴路的架構加上應用在電路當中的有限狀態機，使得操作在1.4GHz時，其峰對峰抖動量只有1.47ps。此晶片是使用台積電90nm CMOS製程，其核心電路面積為0.785平方毫米。

關鍵字

全數位鎖相迴路；寬頻；快速鎖定

並列摘要

In recent years, the trend of IC design goes toward to the system-level and single-chip solution. Therefore, we usually integrate many intellectual properties (IPs) and customized blocks into a single chip, named System-on-Chip (SoC). As a result, the DLLs are usually used to synchronize the timing of the whole system. However, the analog DLLs are more difficult to be implemented and designed in the advanced process nowadays, and suffered from the PVT variations. On the contrary, the digital DLL circuits are simpler and easier for implementation over technologies. Recently, since the demand of memory market increases, the digital DLL is required to have low jitter and wide operating frequency range. Besides, the characteristic of the fast-locking is also important, since some systems have to be synchronized very quickly after the sleep mode. As a result, a wide-range, low jitter, and fast-locking all-digital DLL is proposed in this work. In this thesis, a novel coarse-tune phase generator (CTPG) is proposed to replace the conventional digital-controlled delay line used in the all-digital delay-locked loop. The proposed CTPG not only expands the operating frequency range which is from 120MHz to 1.4GHz but also has the characteristic of fast-locking. The proposed ADDLL achieves a fast-locking time in 7-8 clock cycles irrelevant to input frequency. Besides, the closed-loop architecture and the finite state machine (FSM) implemented to avoid the bubble in the digital control code achieve low jitter, which is 1.47ps at 1.4GHz. The chip was fabricated in the TSMC 90nm CMOS process and occupied 0.785 mm2 active area.

並列關鍵字

All-digital Delay-Locked Loop (ADDLL) ； Wide-Range ； Fast-Locking ； Low Jitter ； Time-to-Digital Converter (TDC)

參考文獻

[1] T. Saeki, et al.,“A 2.5ns Clock Access, 250-MHz, 256-Mb SDRAM With Synchronous Mirror Delay,” IEEE J. Solid-State Circuits, vol. 31, pp. 1656-1668, Aug. 2000.

[2] Y. J. Jeon, et al., “A 66-333MHz 12mW Register-controlled DLL With a Single Delay Line and Adaptive Duty-Cycle Clock Dividers for Production DDR SDRAMs,” IEEE J. Solid-State Circuits, vol.39, no.39, pp.2087-2092, Nov. 2004.

[3] H.Sutoh, K. Yamakoshi, and M. Ino,“Circuit Technique for Skew-Free Clock Distribution,” IEEE Custom Integrated Circuits Conf., pp.163-166, 1995.

[4] G. K. Dehng, et al.,“Clock-Deskew Buffer Using a SAR-controlled Delayed-Locked Loop,“ IEEE J. Solid-State Circuits, vol.35, no.8, pp.1128-1136, Aug. 2000.

[5] Shun-Wen Cheng, “A High-Speed Magnitude Comparator With Small Transistor Count,” IEEE Proceedings of International Conference on Electronics, Circuits and Systems, vol. 3, pp. 1168 – 1171, Dec. 2003.

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一1.47ps低擾動，120MHz - 1.4GHz寬頻且快速鎖定之全數位延遲鎖相迴路

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