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  • 學位論文

百億位元乙太網路接收機的序列–並列轉換器電路之設計

Design on a Deserializer Circuit for the 10GBASE-LX4 Ethernet Receiver

指導教授 : 曹恆偉

摘要


隨著網際網路的快速發展與普及,人們對於網路通信頻寬的需求急遽成長,區域網路的頻寬也已在近幾年內跨入百億位元乙太網路的新紀元。在國際電子暨電機工程師協會所制定的百億位元乙太網路規格中,10GBase-LX4使用低成本的雷射二極體,光二極體及多模或單模光纖作為光通訊的媒介,相信10GBase-LX4的規格將會在下一代乙太網路中扮演主要角色。 在本論文中,依據百億位元乙太網路系統之10GBase-LX4規格,設計一在接收機端的序列–並列轉換器,作為一個資料型式的轉換介面。當由時脈資料回復電路所得到的高速序列資料被輸入後,藉由偵測其同步用字元的出現與否來達成資料的位元組同步,並將資料轉換為較低速的並列形式後輸出。

並列摘要


With the fast proliferation and development of the Internet, the demand for high-speed communication networks has grown progressively. The bandwidth of local area network (LAN) already enters the generation of the 10 Gigabit Ethernet recently. In the standard of IEEE 802.3ae, which is defined for the 10 Gigabit Ethernet, 10GBase-LX4 specification utilizes low-cost laser diodes, optical diodes, and multi-mode or single-mode fibers. 10GBase-LX4 will play an important role in the Ethernet in the near future. In this thesis, first we design a deserializer for 10GBase-LX4 receiver. The deserialzier functions as a data type converter. As a high-speed data stream came from Clock/Data Recovery is input, the deserializer not only achieves byte-level synchronization by detecting the alignment character, but it also converts the high-speed input stream into lower-speed parallel output.

參考文獻


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