考慮效能及可製造性之多階層無格線式全晶片繞線

Multilevel Gridless Full-Chip Routing Considering Performance and Manufacturability

陳泰蓁(Tai-Chen Chen)

指導教授 ： 張耀文

國立臺灣大學/電機資訊學院/電子工程學研究所/博士(2007年)

https://doi.org/10.6342/NTU.2007.03240

摘要

隨著製程技術進入奈米（nanometer）時代，晶片上元件的尺寸縮小到90奈米以下，同時，單顆晶片可容納超過十億個電晶體。再者，元件的最小尺寸比微影技術（lithography）所使用的波長小上許多，因此晶圓上的設計形狀可能有很大的失真（distortion）。為了處理如此龐大又複雜的電路設計，需要發展新的繞線系統（routing system）來處理現代設計的四大挑戰：複雜度（complexity）、可繞度（routability）、晶片效能（performance）以及可製造性（manufacturability）。本篇論文提出了一個多階層（multilevel）無格線式（gridless）全晶片繞線系統以解決這四大挑戰。此繞線系統由三大部分組成：（一）無格線式繞線模型、（二）光學鄰近校正（Optical-Proximity Correction, OPC）模型及（三）多階層架構。
為了解決現代繞線以及奈米電氣效應的問題，電路設計需要使用可變線寬（variable-width）以及可變線距（variable-spacing）。因此，需要無格線式的繞線方法，因為它具有高度的彈性來處理可變線寬以及可變線距。本篇論文提出一個無格線式繞線模型，可以避免最後的繞線路徑違反設計規則（design rule）以及避免產生多餘的線段（wire）。除此之外，提出一個加強的無格線式繞線模型以降低解空間（solution space）及執行時間。實驗結果顯示，所提出的無格線式繞線模型可以達到目前文獻上最好的繞線結果。
由於次波長的微影技術，製造90 奈米以下的元件需要密集地使用解析度增強技術（Resolution-Enhancement Techniques, RET's），而光學鄰近校正是工業界中最常使用的技術。在繞線階段考慮光學鄰近校正，可以大幅減少後佈局（post-layout）階段執行光學鄰近校正的成本。本篇論文提出了一個以規則為基礎（rule-based）以及一個以模型為基礎（model-based）的模型來預測後佈局階段光學鄰近校正軟體的行為，並且把提出的模型整合進入我們的多階層無格線式繞線器以降低光學鄰近校正的成本。實驗結果顯示，所提出的光學鄰近校正模型可以很有效地減少特徵元件（pattern feature）的數量以及邊緣放置誤差（edge-placement error）。
為了解決日益增加的設計複雜度，需要新一代的電子設計自動化工具。本篇論文提出了一個新的V-型多階層架構來提升晶片效能。不同於傳統的多階層架構，V-型多階層架構運作的方式為：由上而下（top-down）的反粗糙化（uncoarsening）接著是自下而上（bottom-up）的粗糙化（coarsening）。在最佳化全晶片效應上，V-型多階層架構比傳統的多階層架構表現得好，主要是因為V-型多階層架構從整體全晶片往局部處理，再從局部往全晶片修正，所以提高了全晶片效應處理的彈性。實驗結果顯示，在擁有較短的互連總線長（total wirelength）、較小的關鍵連線延遲（critical net delay）、以及較小的平均連線延遲（average net delay）下， V-型多階層架構得到目前文獻上最佳的繞線品質。

關鍵字

實體設計 ； 繞線 ； 無格線式繞線 ； 多階層架構 ； 可製造性設計 ； 光學鄰近校正

並列摘要

As technology advances into the nanometer era, chips may consist of billions of transistors, and process geometries shrink to 90 nm and below. Further, the minimum feature size becomes significantly smaller than the lithographic wavelength, and thus design shapes on a wafer may have large distortions. For such large and complex designs, it is desirable to develop a new routing system that can cope with the four major modern design challenges: complexity, routability, performance, and manufacturability. In this dissertation, we propose a multilevel gridless full-chip routing system to handle these four design challenges. The system consists of three major parts: (1) the gridless routing model, (2) Optical Proximity Correction (OPC) modeling, and (3) the multilevel framework.
To handle modern routing with nanometer electrical effects, we need to consider designs with variable wire/via widths and spacings, for which gridless routing approaches are desirable due to its great flexibility. We introduce a gridless routing model that can obtain design-rule-correct paths and avoid redundant wires. Besides, we propose an enhanced model for the gridless routing model to reduce the solution space and the runtime. Experimental results show that the proposed gridless models lead to the best routing solution ever reported in the literature.
Due to the sub-wavelength lithography, manufacturing the sub-90 nm feature size requires intensive use of Resolution-Enhancement Techniques (RET's), among which OPC is the most popular technique in industry. Considering OPC during routing can significantly alleviate the cost of post-layout OPC operations. We present rule- and model-based OPC modeling to predict the behavior of a post-layout OPC tool and incorporate the models into our gridless router to reduce the OPC cost. Experimental results show that the great effectiveness of our OPC modeling in reducing the number of pattern features and edge-placement errors.
To cope with the increasing complexity, electronic design automation tools of very large-scale designs are needed. We present a new ``V-shaped' multilevel framework (called VMF) for performance consideration. Unlike the traditional multilevel framework, VMF works in the V-shaped manner: top-down uncoarsening followed by bottom-up coarsening. The VMF outperforms the traditional one in optimizing global circuit effects, since the VMF first considers the global configuration and then processes down to local ones level by level and thus the global effects can be handled at earlier stages. Experimental results show that the VMF achieves the best published routing quality with less wirelength, smaller critical net delay, and smaller average net delay.

並列關鍵字

physical design ； routing ； gridless routing ； multilevel framework ； design for manufacturing (DFM) ； optical proximity correction (OPC)

參考文獻

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