建立製程偏差模型與積體電路之平行模擬

因應技術不斷進步，許多統計型時序以及製程良率分析演算法相繼被提出，而為了要支援這些演算法，一個準確的空間相關統計模型 (spatial correlation model)是非常必要的。一個沒有彈性的模型除了在模化過程時會有很大的誤差之外，更嚴重的是在我們將此模型導入電路模擬時會導致整個結果完全無法信任。在本篇論文，我們首先提出了一個全新的空間相關統計模型，它不只可以處理一般化的空間相關性問題，而且它還提供了非常精確的解析模型。接著，使用了我們提出的統計模型，我們提出一個考慮相關性的非高斯分佈統計型平行電路模擬演算法(correlation-aware non-Gaussian statistical and parallel circuit simulation algorithm)。我們的電路模擬演算法首先將一個電路切成一些比較小的子電路，然後我們應用多執行緒的技術來平行處理每一個子電路，不只如此，我們還使用了外部記憶體來減少記憶體使用量，再搭配我們所提出的演算法，整體效能幾乎不會因為外部記憶體而有所損耗，記憶體的使用量也因此降低到29%。傳統上為了要模擬製程偏差對電路效能的影響，都是使用蒙地卡羅法 (Monte Carlo simulation)來估計製程偏差的效應，蒙地卡羅法最大的問題就是需要大量的模擬結果來得到可靠的結果，整個模擬過程非常耗時。如果使用我們提出的統計型電路模擬演算法，我們只需經過一次的模擬，就可以由導出的隨機變數直接估計其統計分佈，藉此大大的縮短模擬所需的時間。實驗結果指出，利用我們提出的統計型電路模擬演算法，可以比傳統的蒙地卡羅法快上超過700 倍的時間。

關鍵字

超大型積體電路；製程偏差；統計模型；電路模擬；平行處理

並列摘要

With the significant advancement of statistical timing and yield analysis algorithms, there is a strong need for accurate and analytical spatial correlation models. Inflexibility of the modeling capability could induce errors during statistical modeling and in the worst case induce large errors when the model is further used in circuit simulation. In this thesis, we first propose a novel spatial correlation modeling method not only can capture the general spatial correlation relationship, but also can generate highly accurate and analytical models. We also propose an efficient correlation-aware non-Gaussian statistical and parallel circuit simulation algorithm to combine with the proposed spatial correlation model. Our proposed method first partitions the traditional linear system into several sub-blocks. Then, multi-threading technique is applied to each sub-block simultaneously. Moreover, the efficient out-of-core scheme is proposed to dramatically reduce the memory effort without losing performance. The memory usage of our algorithm can be reduced to 29%. Instead of using expensive Monte Carlo simulation, we simultaneously solve the mean and variance in ordinary equations with quadratic Gaussian random variables. Our experimental results show that our proposed approach can achieve over 700X speed up over fundamental Monte Carlo simulation with just negligible errors.

並列關鍵字

VLSI ； Process Variation ； Statistical Modeling ； Circuit Simulation ； Parallel Computing

參考文獻

[43] Lizheng Zhang, Jun Shao, and Charlie Chung-Ping Chen. Non-gaussian statistical

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[41] Lizheng Zhang, Weijen Chen, Yuhen Hu, and Charlie Chung-Ping Chen. Statistical

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[10] Patrick R. Amestoy, Timothy A. Davis, and Iain S. Duff. Algorithm 837: Amd, an

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建立製程偏差模型與積體電路之平行模擬

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