使用雙迴授路徑組成之鎖相迴路設計製作

在現今無線通訊上，例如:無線區域網路(WLANs)、行動電話及衛星通訊設備…等等，鎖相迴路(Phase Locked Loop,PLL)常扮演著重要的角色。鎖相迴路的功能在於鎖定相位，可以使電路的時脈同步並減少非理想效應所產生的偏差。由於製程的演進及科技的進步，使目前晶片的操作速度越來越快，然而晶片內部的非理想效應會使相位產生偏差延遲，導致所需的資料結果產生錯誤。這時鎖相迴路就可以用來校正減低延遲的時間以確保資料的正確性。在應用上，鎖相迴路在外部輸入較低振盪時脈經由內部時脈合成的功能可以產生一個高速時脈的輸出。而在時脈合成的過程中，穩定時間(Settling Time)與壓控震盪器控制線上的漣波(Ripple)大小常有相當重要的取捨。對於頻率合成器而言，穩定時間對於通道切換的速度有著重要的影響，而壓控震盪器控制線上的漣波則關係著頻率合成器的輸出是否為一穩定的時脈。而如何設計出擁有較快穩定時間及具有穩定的時脈輸出的鎖相迴路是本論文所探討的重點。本論文主題在於使用標準互補式金氧半製程，實現一個有雙回授路徑組成之鎖相迴路。論文內容可以兩個部份，第一部份在第二章，其中分別描述鎖相迴路的原理和分析鎖相迴路整個系統。第三章和第四章為第二部份，敘述了鎖相迴路的電路設計、製作及量測。最後，將在第五章裡做總結。

關鍵字

相位頻率偵測器；電荷幫浦；迴路濾波器；除頻器；死區；劇跳

並列摘要

Phase-locked-loops (PLLs) are widely used in wireless data telecommunications, such as wireless local area networks (WLANs), mobile and satellite communications. In these applications, the PLLs are usually used as a clock synthesis block to generate a high-speed internal clock from an external fixed oscillation source. There is a tight tradeoff between the settling time and the amplitude of the ripple on the VCO control line in the design of phase-locked loops. This tradeoff for phase-locked RF synthesizers limits the performance in terms of the channel switching speed and the magnitude of the reference sidebands that appear at the output. This paper presents a double PFDs PLL approach with a tunable delay unit to produce a small ripple on the VCO control line as well as a low jitter performance metric. Besides, the proposed architecture also provide another benefit that less settling time is required compared to the architecture with only one PFD. Section II develops the fundamental principle for the architecture of the proposed phase-locked loop. The circuit design and simulation results of the presented phase-locked loop are shown in Section III and Section IV, respectively. Finally, a conclusion is given in Section V.

並列關鍵字

Phase Frequency Detector (PFD) ； Charge Pump(CP) ； Loop Filter ； Frequency Divider (FD) ； Dead Zone ； Jitter

參考文獻

[19] Shigura Matusuda, Deborah Brown, Tom Mathews, Ahmed Salem, Bill Burdette, PLL Performance, Simulation, and Design, 2001, National Semiconductor.

[28] K. H. Cheng, T. H. Yao, S. Y. Jiang, and W. B. Yang, “A difference detector PFD for low jitter PLL,” in Proc Int. Conf. on Electronics, Circuits and Systems (ICECS’01), pp. 43-46, Sept. 2001.

[3] B. Razavi, ed., Monolithic phase-locked loop[s and clock recovery circuits. IEEE Press, Piscataway, NJ 1996.

[5] R. J. Baker, H. W. Li, and D. Boyce, CMOS: circuit design, layout, and simulation. IEEE Press, Piscataway, NJ 1998.

[8] B. Chang, J. Park, and W. Kim, “A 1.2 GHz CMOS Dual-Modulus Prescaler Using New Dynamic D-Type Flip-Flops,” IEEE J. Solid-State Circuits, vol. 31, pp. 749-752, May 1996.

國際替代計量

使用雙迴授路徑組成之鎖相迴路設計製作

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