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  • 學位論文

應用於Coarse-Fine時間數位轉換器之增益可調時間放大器

Design of Gain-Adjustable Time Amplifier for Coarse-Fine Time-to-Digital Converters in 0.18 μm CMOS Process

指導教授 : 施鴻源

摘要


隨著科技的發展進步,各種微型化的產品越來越小;越來越快。電晶體的操作速度越來越快,隨之而來的問題,電晶體的操作電壓卻越來越低。使得要在低電壓域(Voltage Domain)設計電路變得越來越難。尤其是在類比電路的設計上,要達到高解析度變得十分困難。反之,由於電晶體的操作速度越來越快,因此在時間域(Time domain)上處理訊號可達到的解析度越來越高。 近幾年時間數位轉換器(Time-to-digital converters, TDCs)被廣泛的使用於量測特定的事件間的時間差量,如射頻全數位頻率合成器、晶片抖動量測、單分子螢光光譜、螢光影像和雷射顯微掃描如。在高速情況下,時脈的量測,資料的傳輸及接收,在傳輸過程中雜訊之干擾問題,是很重要的問題。 此篇論文使用不同以往於數位TA的架構,提出一個類比式的時間放大器架構,在0.18um製程下實現精確並可調整的放大倍率。將此TA架構應用於Coarse-Fine TDC中,將大大提升電路的解析度。

並列摘要


With the improvement of technology, electronic products are miniaturized and are getting faster. Operating speed of transistors is getting faster and faster, with the problem, the operating voltage of the transistor is getting low. Low operating voltage results in difficulty of processing signals with high resolution in voltage domain, especially for analog circuits. On the contrary, transistors featured high speed can process signals with high resolution in time domain. In recent years, TDCs used for detecting time interval of specific events are widely applied in many fields such like all digital PLL, chip’s jitter, single molecule fluorescence spectroscopy, fluorescence imaging and laser scanning microscopy. In high speed situation, there have some very important issues about clock measurements; the data transmission and reception and the noise interference problems. This paper proposes an analog-implemented TA architecture which is different from the past works used a digital architecture of TA to achieve a large and precise time difference amplifying. With applied in a coarse-fine TDC, resolution of the TDC can be greatly enhanced.

參考文獻


[1]M. Crotti, I. Rech and M. Ghioni, “Four Channel, 40 ps Resolution, Fully Integrated Time-to-Amplitude Converter for Time-Resolved Photon Counting,” IEEE Journal of Solid-State Circuits, vol. 47, no. 3, pp. 699-708, Mar. 2012.
[2]M. Lee and A. Abidi, “A 9 b, 1.25 ps Resolution Coarse–Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue,” IEEE Journal of Solid-State Circuits, vol. 43, No. 4, pp. 769-777, April 2008.
[3]P. Dudek, S. Szczepan’ski, and John V. Hatfield, “A High-Resolution CMOS Time-to-Digital Converter Utilizing a Vernier Delay Line,” IEEE Journal of Solid-State Circuits, vol. 35, No. 2, pp. 240-247, Feb. 2000.
[4]S.-K. Lee, Y.-H. Seo, H.-J. Park and J.-Y. Sim, “A 1 GHz ADPLL with a 1.25 ps minimum-resolution sub-exponent TDC in 0.18 um CMOS,” IEEE Journal of Solid-State Circuits, vol. 45, no. 12, pp. 2874–2881, Dec. 2010.
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