應用於生醫之低功耗十二位元分裂式電容連續漸進式類比數位轉換器

A Low Power 12-bit SAR ADC with Split Capacitor Array for Biomedical Applications

黃少宏(Shao-Hung Huang)

指導教授 ： 江正雄

淡江大學/工學院/電機工程學系碩士班/碩士(2012年)

https://doi.org/10.6846/TKU.2012.00351

摘要

隨著電子資訊的發展、科技的進步。現在微電腦系統、VLSI 和 DSP(數位信號處理)技術發展下，數位類比轉換器(Analog to Digital Converter 簡稱 ADC 或 A/D 轉換器)的應用十分的廣泛。評估一個 ADC 轉換器特性有速度（Speed）、耗電量 (Power) 、解析度(Resolution) 以及面積 (Area)。基於現實條件限制下，必須針對應用來做出取捨，設計出最適合的 ADC 轉換器。
本論文所提出 SAR 12-Bit ADC 主要應用在心電圖（ECG）量測的系統，為了能夠長時間的記錄與監測病人的心電圖，捕捉陣性心率失常，所以規格上必須低功耗。使用台灣積體電路的 CMOS 0.18μm 1P6M 標準製程來實現電路，其工作電壓為1.8V，頻寬為500Hz，取樣頻率為2000Hz，設計最大功耗為30uW。

關鍵字

連續漸進式數位類比轉換器 ； 數位類比轉換器 ； 分裂式電容

並列摘要

Under the development of microcomputer system, Very Large Scale Integrated circuit (VLSI) and Digital Signal Processing (DSP), Analog to Digital Converter (ADC) relted applications has been widely used. Speed, resolution, power consumption, and area are the four key specifications while designing ADC. Under the limitations of the actual conditions, trade-off was made within these four specifications in order to design the most appropriate ADC converter. This thesis refers to the 12-Bit SAR-ADC which is mainly used in electrocardiogram (ECG) measurement system. In order to be able to capture the probability of arrhythmia through monitoring and recording ECG for a long period of time, the specifications must be low power consumption. The ADC converter chip proposed by this study was implemented by the TSMC 0.18μm 1P6M standard CMOS process technology. The sample rate is 2000Hz in 500Hz signal bandwidth. The maximum design power is 30μW under 1.8V power supply.

並列關鍵字

SAR-ADC ； successive approximation ADC ； Split capacitive-array DAC

參考文獻

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