群聚法應用分層分區之研究

Research on the Clustering Application of Hierarchical Partition

陳威豪(Wei-How Chen)

指導教授 ： 饒建奇

淡江大學/工學院/電機工程學系碩士在職專班/碩士(2015年)

https://doi.org/10.6846/TKU.2015.00604

摘要

由於現在的科技越來越進步，人們的渴望的需求也慢慢的提升，積體電路設計來滿足未來生活機能，以40奈米慢慢的提高到16奈米，由於現在三維積體電路堆疊技術開啟了科技的新方向，使得在一些生活機能裝置的發展對積體電路設計要求也會越來越多也會越做越小來滿足生活機能。現在的三維積體電路比之前的二維積體電路設計不僅可以加入更多的電晶體，提升連線密度、減小外觀尺寸、提升效率、降低生產費用、不限制裸晶、減少繞線長度、堆疊來達到製程技術，而且現在的三維積體電路堆疊技術連接的分別為矽穿孔(Through silicon via ,TSV)是比較常用的方式，由於為了讓矽穿孔(Through silicon via ,TSV)數量減少來達到成本上的考量，以及現在三維積體電路在設計上仍難要如何解決散熱上的問題以及避免漏電流的問題。

關鍵字

群聚 ； 貪婪 ； 平面規劃

並列摘要

more and more technological advances, people's desire demand has slowly improved, integrated circuit design to meet future life functions, slowly at 40 nm to 16 nm, due to the now three-dimensional stacked integrated circuits technology opens up new directions in technology, making some life functions in the development of the integrated circuit device design requirements will be more and more will get smaller to meet life function. Dimensional integrated circuit design now than before the three-dimensional integrated circuits can not only add more transistors to enhance the connection density, reducing the appearance of size, improve efficiency, reduce production costs, does not limit the die, reducing the winding length stacked to achieve process technology, and now the three-dimensional integrated circuit stacking technology connections are silicon perforation (Through silicon via, TSV) is a more common way, because in order to make silicon perforation (Through silicon via, TSV) to reduce the number to achieve cost considerations, and now three-dimensional integrated circuits is still hard to be on how to solve the problem in the design of the heat and to avoid leakage problems.

並列關鍵字

Clustering ； greed ； floorplan

參考文獻

[16] 李佶，“Simultaneous layer-aware and position-aware partitioning for 3D VLSI” 台北科技大學，民國102年6月

[18] Tan Yan, Qing Dong, Yasuhiro Takashima and Yoji Kajitani, “How Does Partitioning Matter for 3D Floorplanning?,” Proceedings of the ACM Great Lakes symposium on VLSI , 2006, pp. 73-78

[8] Y. Y. Liauw, Z. Zhang, W. Kim, A. El Gamal, and S. Wong, “Nonvolatile 3D FPGA with monolithically stacked RRAM-based configuration memory,” in Proc. Int. Solid-State Circuit Conf., Feb. 2012,pp. 406–408.

[11]D. F. Wong, and C. L. Liu, “A New Algorithm for Floorplan Design,”IEEE Proc. DAC, pp.101–107, 1986.

[12]Chang-Tzu Lin, De-Sheng Chen, Yi-Wen Wang., “GPE: A New Representation for VLSI Floorplan Problem,”IEEEProc.ICCD, pp. 531 -533, 2002.