In this thesis, proposed ant colony algorithm based on a SOPC (System on a Programmable Chip) technique on the FPGA chip. In the design and implementation of ant colony algorithm based on a SOPC (System on a Programmable Chip) technique is applied to design two processing method: (1) Selecting path, (2) Path analysis. Selecting path belongs to the pre-processing of the ant colony algorithm takes a longer computing processing time, so design into a hardware circuit, in order to speed up processing. (2) path analysis will be to the C language software in the NIOS II processor. Experimental results found in this paper to the processing time can be less accurate path information.