運用格子化通道繞線模型於標準單元電路設計之兩層繞線演算法

隨著半導體製程的日益進步，數位電路所面臨的繞線問題變得越來越複雜，伴隨而來的問題就有電路是否能完成100%繞線以及所需要用到的總繞線面積大小…等。如果一個電路有不能完成繞線的部份，繞線器將會花費相當多的時間在做重新繞線的工作上，所以要在元件放置之後就要開始分析繞線所需的繞線資源以及其他繞線時所需要的相關資訊。在使用標準電路單元設計電路時，我們首先會先將設計完的電路，找出其對應的標準電路元件，然後先做初步的電路元件放置之後，再進行繞線的動作。在此篇論文中，我們使用格子化模型來作繞線的依據，使用格子化模型的好處是它會使繞線的複雜度降低，只要依照格子化模型去繞線，就不會有設計規則校正 (DRC) 違反的問題，這也會使得設計電路的時間與繞線難度大大的降低。接下來，我們將以此格子化模型為基礎，來處理繞線時可能發生的不可繞的狀況。我們將提出一個新的方法，來解決電路不可繞的情形。我們將在放置電路元件之後，取得一些繞線所需要的相關資訊，在從這些資訊中去找出在繞線時，可能會出現的不可繞的狀況，然後搭配我們所提出的演算法，進一步地去預先解決不可繞的電路，使用我們的方法，可以達成100%的繞線結果，並且能在線性時間內完成繞線。在完成所有的繞線之後，我們可以選擇性的去增加一些空間，減少通道數目的使用，來將通道數目做一個最佳化的動作，這能針對一些需要較少通道的電路，有較大的幫助。最後，我們使用ISCAS’85 benchmarks 來模擬我們的結果，ISCAS’85 benchmarks 是一套組合邏輯電路，我們可以知道電路內含的元件數目以及各個元件中的輸入、輸出腳數目。模擬結果，我們平均需要增加6.34%的面積，就可以完全解決電路中不可繞線的部份，並且能保證電路能100%的完成繞線。

關鍵字

超大型積體電路實體設計；標準單元設計；通道繞線

並列摘要

In recent year the advance of semiconductor manufacturing technology has led to a great development, the routing problems of digital circuit design become more and more complex. The following problems that are the circuit whether it can achieve 100% routing or not and the need of total routing area…etc. If the circuit has the segments that can be route, the router will spend much more time on re-route. Therefore, after placed the components we begin analyzing the routing data and other related data that are need for routing. Using standard cell style to design digital circuits, the first we will map the designed circuit in standard cell library and we will place the components preliminary then route the nets. In this paper, we use the grid based routing model to deal with the routing problems. The advantage of using grid based routing model is the model can reduce the complexity of routing. If the router routing the circuit base on this routing model, it will not violate the design rules check (DRC) and it will reduce more the design time and design difficulty. Following, we will base on the grid routing model to deal with the unrouted problems that maybe occur during routing the nets. We propose a novel approach to solve the unrouted problems. After we placed the components of circuit, we will get some related data that are need for routing and we will find the unrouted conditions from these data beforehand. After that using our propose algorithm to solve the unrouted circuits in advance and using our approach can achieve 100% routing results and it can finish in linear time. Complete all of the nets routing, we can add some space selectively to reduce the numbers of channel tracks. Optimize the numbers of channel tracks that is helpful to reduce the channel height. Finally, we use the ISCAS’85 benchmarks to simulate the results. The ISCAS’85 benchmarks are a group of combinatorial logic circuits that we know how many components、inputs and outputs of circuits. In the simulation results, the area overhead only increase 6.34% in average to solve all of the unrouted segments and it can guarantee to achieve 100% routing.

並列關鍵字

VLSI physical design ； Standard cell style ； Detail routing

參考文獻

[1] Bass, M.J.; Christensen, C.M., “The future of the microprocessor business”, IEEE Spectrum, Vol.39, April 2002, pp. 34-39.

[3] Lauther, U., “A Min-Cut Placement Algorithm for General Cell Assemblies Based on a Graph Representation”, Design Automation, 1979. 16th Conference on, June 1979, pp.1-10

[6] Fischer, H.; Pschunder, W., “Low-cost solar cells based on large-area unconventional silicon”, Electron Devices, IEEE Transactions on, Vol.24, April 1977, pp. 438-442.

[8] Leong, H.W.; Liu, C.L., “Discretionary channel routing”, IEE Proceedings-Circuits, Devices, and Systems, Vol.135, April 1988, pp. 45-57.

[10] Yang Cai; Wong, D.F., “Optimal via-shifting in channel compaction”, Design Automation Conference, EDAC. Proceedings of the European, March 1990, pp. 186-190.

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運用格子化通道繞線模型於標準單元電路設計之兩層繞線演算法

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