- 學位論文
延遲鎖定迴路應用於寬頻快速鎖定之倍頻器設計
Design of a Fast-Locking DLL-Based Frequency Multiplier for Wide-Range Operation
摘要
系統晶片的設計通常需要使用多重相位時脈，鎖相迴路(Phase-Locked Loop, PLL)可以提供一個良好的時脈同步處理機制。然而，PLL本身是高階的迴路且VCO的時脈抖動(jitter)累積特性，會使得高效能的PLL設計變的更加複雜。因此，在延遲鎖定迴路(Delay-Locked Loops, DLL)中，由於jitter不會累積於電壓控制延遲線(Voltage-Controlled Delay Line, VCDL)，且其本質上是個穩定的一階系統，因此，DLL在使用上日益廣泛。 雖然VCDL不會有jitter累積的問題，但在整個DLL迴路之中，仍會有元件誤差及走線延遲所產生的jitter量。所以在本論文的第一個部份，我們提出了雙迴路延遲鎖定迴路架構來改善這個問題。整個電路我們使用0.35um CMOS technology來製作，其操作範圍可由250MHz~ 450MHz， 而模擬的cycle-to-cycle jitter在250MHz時為21ps。 另外，當DLL啟動之後，往往需要一段時間才能鎖定輸出，這在系統中局部電路改變頻率時，將會拖慢系統的穩定時間。所以我們提出了一個可程式化的控制電路提供一個適當的電壓給回授濾波器，以加速DLL鎖定的時間。此外，我們同時提出一個新式的倍頻器，它不僅具有較少的元件，且其輸出的頻率可大幅的提升。在此倍頻器之中，VCDL採用虛擬差動延遲元件(pseudo-differential delay cells)的差動輸出當作倍頻器的輸入，藉以得到近似50%的工作週期(duty cycle)時脈。這一個電路是利用0.18um 1P6M CMOS製程實現，由模擬結果得知，DLL可操作頻率的範圍為從200MHz到2GHz。鎖定時間最少僅需要6個週期，且在320MHz時模擬的cycle-to-cycle jitter為31ps，此時功率消耗為25mW。
並列摘要
The multiphase clocks are usually required in a system-on-chip design. The phase-locked loop (PLL) provides a well locking loop for the synchronization of clocks. However, the inherent high-order loop in the PLL and the jitter accumulation of the VCO make it difficult to design a high-performance PLL. Consequently, the delay-locked loop (DLL) is increasingly preferred rather than PLL due to no jitter accumulation in the voltage-controlled delay line (VCDL) and it is inherently a stable first-order system. Although the problem of jitter accumulation does not exist in the VCDL, there remains some jitter resulted by the device mismatch and loop delay in DLL loop. Thus, in the first section of this thesis, we propose a new dual-loop DLL to reduce the resulted jitter. The prototype circuit has been fabricated in 0.35μm 2P4M CMOS technology. The proposed DLL can operate with the input frequency from 250MHz to 450MHz. The simulated cycle-to-cycle jitter of the DLL is 21 ps at a 250MHz of input frequency. Furthermore, the DLL often needs a lot of time to lock the output frequency while a subsystem changes the reference frequency. Therefore, in the second part of this thesis, a programmable controller combined with a voltage reference circuit is proposed here to provide the loop filter a proper voltage to speed the locking of the DLL. Besides, we also present a new frequency multiplier, which not only processes less number of devices but also increases the output frequency of the DLL substantially. For such a frequency multiplier, we use the differential output of the VCDL, which adopts pseudo-differential delay cells, as its input to derive a clock with a roughly 50% of duty cycle. The circuit has been fabricated in 0.18μm 1P6M CMOS technology. From the simulation results, the proposed DLL-based frequency multiplier can operate Sin a wide range from 200MHz to 2GHz. Meanwhile, at the frequencies in such range, the minimum locking time of the DLL can be as less as six clock cycles. The simulated cycle-to-cycle jitter of the DLL is 31 ps at a frequency of 320MHz. The power consumption of the presented DLL is 25mW with a 1.8V supply voltage.
參考文獻
延伸閱讀
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