近年來,具有部分動態可重組系統(Partial Dynamic Reconfigurable Systems, PDRS)的現場可程式化閘陣列(Field Programmable Gate Array, FPGA)成為了重要的研究題目。PDRS FPGA具有在同一時間允許平行執行多個任務(Task),並且能在不影響其它任務的執行下,即時地替換部分FPGA區域的任務功能,此舉可大幅增加系統在設計上的彈性、有效減少電路的佔用的面積、並且可以降低功率。但是伴隨著系統的彈性增加,使硬體任務也產生像是作業系統中的多線程(Multithreading)問題,因此對於相依性系統任務的排程也越顯重要。為了能夠完全發揮動態可重組FPGA的特性,我們設計了一個即時硬體排程器,來提升系統任務的排程效率,以提高硬體的使用率與縮短系統任務所需要的執行時間。本文在具有硬體內文切換(Hardware Context-Switch)的自我可重組(Self-Reconfigurable)系統上,使用硬體描述語言(Verilog HDL)設計一個部分動態可重組系統硬體排程器,來解決啟發式演算法不適合處理之動態相依性任務排程。最後本文使用TGFF (Task Graph for Free) 產生隨機任務來驗證本方法之有效性。從實驗結果分析中,我們提出的硬體排程器可以有效減少7.07%系統執行時間與28.79%任務配置時間。
Today’s Field Programmable Gate Arrays(FPGAs) with Partial Dynamic Reconfigurable Systems(PDRS) have been became an important research topic. PDRS FPGAs allow executing multitasks at one time, and switching the task functionality of partial FPGA without influencing other tasks execution. This method can increase the flexibility of system design, reduce the area of the circuits and improve the power consumption of systems. With increasing flexibility, there are produced some problems. Therefore the scheduling of system tasks is more and more important. In order to take full advantage of dynamically reconfigurable FPGA, we designed a real time hardware scheduler to optimize task scheduling system, and to improve hardware utilization and shorten the execution time required for the task. This article uses Verilog HDL to design a PDRS hardware scheduler with hardware context-switch. To solve that heuristic algorithms face difficulties in dealing with nondeterministic systems whose dynamic characteristics. The proposed method has been verified with Task Graph for Free(TGFF). Experiment results show that the proposed hardware scheduler reduces 7.07% on system execution time and 28.79% on the configuration time of bitstreams.