應用在WCDMA RF-repeater回授訊號消除模組之硬體設計與實現

本研究以自適應回授訊號干擾消除技術為基礎發展高增益WCDMA系統之中繼器(Repeater)，以達到除去回授(Feedback)訊號，以優化使用高增益中繼器之通訊品質。研究採取硬體描述語言HDL撰寫FPGA發展回授訊號消除模組(Echo-Cancellation Module)，此發展模組包含自適應回授訊號消除器、半波濾波器(Half-band filter)、低通濾波器(Low-pass filter)、降頻器(Down sample)、升頻器(up sample)、鎖相環迴路(PLL)、以及A/D、D/A等元件，其中自適應回授訊號消除器以pipeline技術實現LMS、NCLMS、DLMS、PIPLMS等演算法。本研究結果由訊號產生器、頻譜分析儀和Altera DE2-115 FPGA平台驗證具回授訊號消除之WCDMA中繼器。所設計之模組操作增益可達Excess isolation -10dB。

關鍵字

中繼器；回授訊號消除； FPGA ； Verilog HDL ；最小均方演算法

並列摘要

In this thesis, we develop a echo-cancellation module (ECM) for high-gain in-band repeater in WCDMA systems. Baseband signal processing along with adaptive signal processing technology is utilized and implemented on FPGA boards. The designed ECM includes an adaptive feedback signal canceller, half-band filters, low-pass filters, down sample converters, up sample converters, phase lock loops (PLL), analog to digital (A/D) convernters, and digital to analog (D/A) converters. The implemented algorithms in the feedback signal canceller includes the Least Mean Squares(LMS), Non-Canonical Least Mean Squares(NCLMS), Delay Least Mean Squares(DLMS), and Pipeline Least Mean Squares(PIPLMS) algorithm.The designed ECM is examined by using signal generator, spectrum analyzers and Altera the DE2-115 FPGA platform, to demostrate a high-gain WCDMA repeater with the feedback signal cancellation functionality. The designed ECM can operate at the excess isolation up to -10dB.

並列關鍵字

RepeaterEcho-Cancellation ； FPGA ； Verilog HDL ； LMS

參考文獻

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國際替代計量

應用在WCDMA RF-repeater回授訊號消除模組之硬體設計與實現

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