具有差額循環排程之ATM與Ethernet封包處理晶片設計與實作

Design and Implementation of the Packet Process ASIC with Deficit Round Robin for ATM and Ethernet

王俊華(Chun-Hua Wang)

指導教授 ： 馬尚智

共同指導教授 ： 宋國明

國立臺北科技大學/電資學院/電機工程系研究所/碩士(2014年)

摘要

未來網路傳輸流量將大幅上升，在有限的網路資源下，資料在傳輸過程中的遺失影響將因為需求量增加而越趨嚴重；本論文著重在排程處理的研究，設計與實現封包處理晶片，期能達到更有效率及更公平的傳輸效果。首先對傳統的先進先出排序機制(FIFO，First In First Out)進行改進，讓封包控管更有效率；其次，搭配差額循環執行排序機制(DRR，Deficit Round Robin)，並以資料暫存於記憶體(Memory)的方式來取代微處理器。藉此，不僅可以暫存資料封包，也利於往後對封包進行確認與校正等工作。
該晶片系統是利用硬體描述語言來實現封包處理模組差額循環，取代一般橋接器中的先進先出排程機制，並整合ATM細胞與Ethernet訊框間之UTOPIA轉換介面傳送端，前端的差額循環模組給予網際網路一個流量管理機制環境，每一個佇列賦予不同的權重值，權重值越高能傳輸的流量越多，可實現低延遲、低遺失率的封包處理模組。最後，以現場可編程邏輯閘陣列開發版(Altera DE3)驗證無誤後，以TSMC之0.18-μm製程進行合成，即經過Synthesis、DFT、APR、DRC/LVS等流程製作出專用晶片(ASIC)，其邏輯閘數(Gate Count)約為37,000，動態功率約為8.6mW。

關鍵字

先進先出排序 ； 差額循環執行排序 ； 乙太網路 ； ATM網路 ； 現場可編程邏輯閘陣列

並列摘要

Network traffic flow will rise sharply in the future. In limited network resources, the effects of losing data during transmission will be growing worse because the requirement increases. The thesis emphasizes the research of the scheduler processing. The chip is designed and implemented to process the packet. We expect to achieve the more fair and efficient transmission effect. First, the original FIFO(First In First Out) is improved. It makes packet management more efficient. Second, the collocating DRR works without microprossor, but also be easy to check and correct the proceed packet. With this arrangement, one can not olny same the data packet, but also be easy to check and correct the proceed packets.
The chip achieves the packet process module DRR with hardware describe language which is used to give up the FIFO mechanism in bridge, and integrate UTOPIA(Universal Test and Operations PHY Interface for ATM) which is the transformed interface of the ATM Cell and the Ethernet packet. The front-end DRR module give Internet a flow management mechanisms environment. Usually, the data contain different weight in the DRR queue. That is, the higher weighted value is the higher the priority is to transmit data.. The proposed DRR can complete the packet process module under low delay and low loss. Finally, an Altera DE3 of FPGA (Field Programmable Gate Array) is adopted to verify the designed function; and that the TSMC 0.18-μm CMOS technology is selected to implement the ASIC after the following proceduce. Including the Synthesis、DFT(Design For Testability)、APR(Auto Place and Route)、DRC(Design Rule Check)、LVS(Layout Versus Schematic), has been completed. According to simulation results, the proposed ASIC performs with the gate count of 37,000, and the dynamic power of 8.6mW.

並列關鍵字

First In First Out ； Deficit Round Robin ； Ethernet ； ATM Network ； Field Programmable Gate Array

參考文獻

[20] 楊忻曄，以FPGA設計與實現DRR的有效公平序列，碩士論文，國立台北科技大學，台北，2010。

[10] 張彥仕，封包處理與分類晶片的設計與實作，碩士論文，國立台北科技大學，台北，2012

[9] 李璟祥，具有格式轉換介面之ATM與Ethernet封包處理晶片設計與實作，碩士論文，國立台北科技大學，台北，2013

[1] T. Wolf, and W. Ning, “Runtime support for multicore packet processing systems,” IEEE Network Magazine, vol. 21, no. 4, 2007, pp. 29-37.

[2] G. M. Sung and H. Y. Hsieh, “A novel bridge chip between an ATM and Ethernet for ADSL in home networks,” IEEE Transactions on Consumer Electronics, 2009, pp.1200-1207.