改良式低功率六位元快閃式類比數位轉換器

類比數位轉換器在今應用上日趨廣泛，其應用上分為：解析度高，以三角積分類比數位轉換器為主。解析度和速度中則以導管式類比數位轉換器為主。速度高則以快閃式類比數位轉換器為主，其轉換速度可達每秒幾百萬取樣頻率到幾億取樣頻率左右，故轉換速度相當快速。但是對一個N位元的快閃式類比數位轉換器而言，Ｎ位元越大其所面對的面積卻呈現2N成長，且伴隨大面積而來的問題就是高功率消耗的問題。在本論文中提出了改良式低功率之方法於快閃式類比數位轉換器。在設計結構上，我們使用了三個比較器來分成四區當觸發，藉此來控制時脈信號是否能進入比較器，同時配合改良式低功率方法的觀念，在一個時脈週期裡，只讓二區的比較器工作，以達到降低功率消耗之目的。整個晶片以台灣積體電路製造公司 TSMC 0.35 µm 2P4M CMOS製程來實現。根據模擬結果，其所得到的功率消耗為16.9mW，比一般傳統式71.72mW約可節省76.5%的功率消耗。其工作電壓採用3.3伏特，以2百萬赫茲取樣頻率下，類比輸入範圍從1.1伏特到3.1伏特下可得其有效位元數為5.754。晶片面積包含I/O Pad總共為 0.8 *1.4 mm2。

關鍵字

快閃式類比數位轉換器；比較器

並列摘要

Analog-to-digital converter is widely used today, based on its application. For the high resolution, the sigma delta analog-to-digital converter is the main role. For the medium resolution and speed, the pipelined analog-to-digital converter is the main role. In addition, for the high speed, the flash analog-to-digital converter is the main role and their converting speeds are from MHz sampling frequency to GHz sampling frequency. Although their converting speeds are really fast, as an N-bit flash analog-to-digital converter, N-bit number increases which also increase its area by 2N. Therefore, the power consumption is large. In the thesis, we have proposed a new method to improve the power consumption for the flash analog-to-digital converters. We use three comparators in our design to divide next stage into four sections and control timing signal whether can proceed to the comparators or not. Within a timing period, only two sections of the comparators are allowed to operate, which achieve the aim of the low power consumption. TSMC 0.35um 2P4M CMOS process is used in the design. According to the simulation result, the power consumption is 16.9mW, which saved by 76.5% from the conventional design, which consumes 71.72mW. And its operating voltage is 3.3 Volts. Under 200MHz sampling frequency and within the range of analog input, from 1.1 Volts to 3.1 Volts, the ENOB of 5.754 can be obtained. The area of the chip is 0.8mm*1.4mm, which includes I/O Pad.

並列關鍵字

Flash Analog-to-Digital Converter ； Comparator

參考文獻

[17] Sanroku Tsukamoto, William G. Schofield and Toshiaki Endo, “A CMOS 6-b, 400-MSample/s ADC with Error Correction”, IEEE journal of Solid-State Circuit, Vol. 31, No. 11, pp. 1931-1836, Dec. 1996.

[1] C. L. Portmann and T.H.Y. Meng, “Power-efficient meta-stability error reduction in CMOS flash A/D converters,” IEEE Journal of Solid-State Circuits, Vol. 31, Aug 1996, pp. 1132–1140

[2] K. Uyttenhove, A. Marques, and M. Steyaert, ”A 6-bit 1 GHz acquisition speed CMOS flash ADC with digital error correction,” Custom Integrated Circuits Conference, May 2000, pp. 249–252.

[3] B. Yu. and Black W. C. Jr., ”A 900 MS/s 6b interleaved CMOS flash ADC,” IEEE Custom Integrated Circuits Conference, May 2001, pp. 149–152.

[4] M. Choi and A. A. Abidi, “A 6-b 1.3-Gsample/s A/D converter in 0.35-μm CMOS,” IEEE Journal of Solid-State Circuits, Vol. 36, Dec. 2001, pp. 1847–1858.

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改良式低功率六位元快閃式類比數位轉換器

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