奈米超薄氧化層PMOS元件之高閘極漏電流特性描述與分析

由於半導體產業的技術不斷精進，為了有效降低晶片的製造成本及提昇其操作性能，因此元件的尺寸不斷地微縮以期望符合甚至超越各相關研究發展機構所訂定的技術時程。在MOSFET元件裡，不僅其通道長度微縮至奈米數量級，其絕緣氧化層更薄至數顆原子直徑大小的超薄厚度。以現今的半導體製造技術而言，65nm~50nm的製程技術為目前企業界與學術界共同的研發目標，在這奈米元件製程世代裡，為使微縮後的奈米元件仍保留所需的元件特性，超薄的氧化層已成為不可或缺的製程條件。然而，在氧化層厚度小於2.0nm後，元件的閘極穿隧電流將愈來愈大，而且穿隧電流隨著氧化層厚度的線性微縮卻是以非線性的指數等比效應劇烈驟升。穿隧電流不僅造成元件操作時多餘的功率消耗，更劇烈影響了元件原有的電性與物性，對與元件的參數萃取及產品可靠性分析也造成相當大的干擾。本論文針對超薄氧化層所造成的相關元件漏電流作深入的研究以及探討，提出了Gate Current Induced Punch-through Model (GCIP Model) 來描述其電流行為。並於不同的實驗條件下探討GCIP Model與通道長度、氧化層厚度之間的正負相依性。另外，高閘極漏電流亦造成閘極電容值萃取上的困難，隨著氧化層的愈來愈薄，閘極穿隧電流嚴重影響閘極電容值的精確值，這樣對閘極電容值的失真效應也深切影響到電子電路工程的設計和應用。對於此現象，論文中也提出相關的研究，並試圖找尋其補償機制。超薄氧化層所造成的高閘極漏電流對於元件製造技術與電子電路的設計應用的確產生相當大的困擾，此一技術瓶頸若能找出有效的解決方案，半導體奈米單晶片產業將會有顯著的突破。這也將使促進產業起飛的莫爾定律在未來的10-20年裡繼續適用。

關鍵字

超薄氧化層；閘極漏電流；奈米金氧化半導體場效電晶體元件

並列摘要

Owing to the device’s shrinking down to nano scale, semiconductor MOS device is now getting into the deep sub-micron regime. As the roadmaps’ expectancy of many related powerful authorities in this semiconductor technology field, the channel length of nano MOS device is shorter than 100 nm accompanied its gate oxide thickness being thinner than 2.0nm. Such a deep sub-micron MOSFET is the most advanced product of coming nano device generation. Meanwhile, the ultra-thin gate oxide layer of this nano scale device brings lots of issues and bottlenecks in device processing, design, performance modeling, characterization, parameter extraction and so forth. This thesis proposes some related researches and discussions to describe and characterize the nano device’s characteristics, inclusive of high gate oxide leakage current, tunneling leakage current, punch-through current, I-V behaviors, reliability, stress condition and so on. We know, in/after 90nm manufacturing generation, there will be more and more technology skills and key-issues waiting for us to improve even completely solute. Hope our research results could provide some contribution to the final nano-issued-solution especially on ultra thin gate oxide leakage issue.

並列關鍵字

Ultra-thin gate oxide ； Gate leakage current ； Nano PMOSFET device

參考文獻

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[8] W. Kirklen Henson et al., “Analysis of Leakage Currents and Impact on Off-State Power Consumption for CMOS Technology in the 100-nm Regime”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 47, NO.7, JULY 2000.

[9] Jordi Sune and Ernest Wu, “Statistics of Successive Breakdown Event for Ultra-thin Gate Oxides”, IEEE, IEDM 2002, pp. 147-150.

[10] Steve S. Chung et al., “A Novel and Direct Determination of the Interface Traps in Sub-100nm CMOS Devices with Direct Tunneling Regime (12~16A) Gate Oxide”, 2002 Symposium On VLSI Technology Digest of Technical Papers.

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奈米超薄氧化層PMOS元件之高閘極漏電流特性描述與分析

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