透過您的圖書館登入
IP:44.200.240.205
  • 學位論文

具不同Si-Cap厚度的SiGe源/汲極應變PMOSFETs之特性分析

Characteristics of SiGe Source/Drain Strained PMOSFETs with Different Si-Cap Thickness

指導教授 : 黃恆盛 陳雙源

摘要


SiGe源/汲極(SiGe source/drain)應變技術,是將MOSFET源極與汲極的矽蝕刻某一深度之後,再重填矽鍺原子。它利用矽與鍺原子的晶格常數不匹配,造成通道內的矽原子受擠壓產生應力,提升載子遷移率,來增強電晶體的效能。 有文獻探討過單軸矽鍺源/汲極對不同閘極長度電晶體性能的影響,但探討同時使用雙軸應變及薄Si-Cap厚度(9、24、39 Å)的並不多。因此在本篇論文中,我們研究含有雙軸應變以及單軸矽鍺源/汲極在不同的薄Si-Cap厚度之下,對於不同閘極長度的電晶體性能影響,並分析Si-Cap太薄產生的問題。另外,因為使用應變矽技術,使得傳統MOSFET的原理與模型(BSIM model,channel-resistance method)變得難以適用,論文中也提出解釋。 經由本研究發現,隨著Si-Cap厚度愈薄,長通道電晶體性能愈提升,這是由於載子走矽鍺通道的比例較大以及雙軸應變的緣故;短通道時,Si-Cap受到SiGe源/汲極擠壓的應力相對變大,使得Si-Cap與介電層之間產生大量缺陷,尤其在Si-Cap=9 Å時,造成電晶體性能反而降低;漏電流也是隨著Si-Cap厚度減少而增加。因此建議Si-Cap的厚度至少要大於24 Å才行。 本研究也探討在線性區以及飽和區的載子遷移率。大多數研究探討遷移率都是利用電導(transconductance)方式求出,然而元件實際運作卻是在電場較高的飽和區,因此探討載子遷移率的提升必須從飽和區著手。由實驗發現,與控制樣本比較,應變矽pMOSFET飽和區的遷移率增加約只有線性區最大轉導所求之遷移率增加的一半,顯示有飽和速度或其他效應的限制。

並列摘要


SiGe source/drain strained-Si technology involves etching out the source/drain area of a pMOSFET and replacing it with SiGe. The device performance can be improved due to the lattice mismatch between silicon and germanium which makes the silicon in channel generating compressive strain. Previous literatures have revealed the effect of MOSFETs with different gate length with uni-axial SiGe-S/D strain. But the studies of pMOSFETs having bi-axial strain using very thin Si-cap thickness and SiGe-S/D simultaneously haven’t been much investigated yet. In this work, we examine and analyze the characteristics of devices containing bi-axial and uni-axial SiGe-S/D strain in various gate lengths with different thin Si-cap thickness (9, 24, 39 Å). Besides, discussion and explanation of the difficulty in applying traditional silicon device models and theorems (BSIM model, channel-resistance method etc.) because of using strain technique are also provided in this thesis. The experimental results show that in long channel, with Si-cap thickness becomes thinner, the device performance enhances more. This is thanks to both the hole-population distribution across the Si-cap/SiGe-channel layers during inversion and hole mobility enhancement in the global strain channel. In short channel, Si-cap encounters seriously compressive stress and generates certain amount of defects. Especially when Si-cap= 9 Å, performance of the pMOSFETs reduces instead. The gate leakage current increases while Si-cap thickness decreasing. Therefore, this study suggests that Si-cap thickness is required to be more than 24 Å at least. This research also investigates the carrier mobility in linear and saturation region. Most research used to extract the carrier mobility by trans-conductance method. However, most MOSFETs actually operate in saturation region with high electric field. Therefore, it is important to extract carrier mobility from saturation region. By comparing with Si control devices, the mobility enhancement of strain pMOSFETs extracting by Idsat method is approximately an half to that by gm maximum method. This result shows that there are factors, such as velocity saturation, limiting the mobility enhancement in saturation region.

參考文獻


[1-2] C. K. Maiti, “Strained-Si Heterostructure Field Effect Devices: Strain-Engineering in CMOS Technology,” Physics of Semiconductor Devices, 2007. IWPSD 2007.
[2-1] S. H. Olsen, A. G. O’Neill, S. Chattopadhyay, L. S. Driscoll, et al., “Study of Single- and Dual-Channel Designs for High-Performance Strained-Si-SiGe n-MOSFETs,” IEEE Transactions on Electron Devices, Vol. 51, No. 7, July 2004.
[2-2] J. L. Liu, C. D. Moore, G. D. Uren, Y. H. Luo, et al., “A surfactant-mediated relaxed Si0.5Ge0.5 graded layer with a very low threading dislocation density and smooth surface,” Applied Physics Letters, Vol. 75, P. 1586, 1999.
[2-3] Y. H. Luo, J. Wan, R. L. Forrest, J. L. Liu, et al., “Compliant Effect of Low-Temperature Si Buffer for SiGe Growth,” Applied Physics Letters, Vol. 78, P. 454, 2001.
[2-4] Z. Y. Cheng, M. T. Currie, C. W. Leitz, G. Taraschi, et al., “Electron Mobility Enhanvement in Strained-Si n-MOSFETs Fabricated on SiGe-on-Insulator (SGOI) Substrates,” IEEE Electron Letters, Vol. 22, P. 321. 2001.

延伸閱讀