利用模擬分析具環形及淺摻雜汲極佈植之90 nm nMOSFETs的Ion / Ioff

Using Simulation to Analyze the Ion / Ioff of 90 nm nMOSFETs with Pocket and LDD Implants

陳映璁(Ying -Tsung Chen)

指導教授 ： 黃恆盛、陳雙源

國立臺北科技大學/機電學院/機電整合研究所/碩士(2007年)

https://doi.org/10.6841/NTUT.2007.00220

摘要

由於製程技術不斷的進步，金氧半場效電晶體（Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET）的閘極長度（gate length）也持續不斷地在縮小，為遏止短通道效應（Short Channel Effect, SCE）及熱載子效應(hot-carrier effect)，現在的製程皆有採用環型佈植（pocket implant）和淺摻雜汲極（Lightly Doped Drain, LDD），不過這些措施也使MOSFET有反轉短通道效應(reverse short channel effect)及增加通道電阻等缺點。
因此，為了讓元件的設計者可以去調整並預測短通道nMOSFETs的行為，本研究使用ISE TCAD 10.0版來模擬nMOSFET，以不同的閘極長度及環形和LDD佈植的能量與劑量，紀錄及分析驅動電流（Ion）和截止電流（Ioff）的變化，經由定義Ion和Ioff與閘極長度之關係曲線的特徵值，再推導經驗公式，以做為未來元件工程師設計MOSFET時，調整環形和LDD佈植能量與劑量的參考。也就是說，元件工程師只需將所欲元件的特徵值，代入本研究所提出的經驗方程式，再經由解方程式，即能快速地得到所對應的環型與LDD佈植的能量與劑量值。

關鍵字

金氧半場效電晶體 ； 閘極長度 ； 短通道效應 ； 反轉短通道效應 ； 環型佈植 ； 淺摻雜汲極 ； 臨界電壓 ； 驅動電流 ； 截止電流（關閉電流）

並列摘要

Due to the nonstop progress of process technology, the gate lengths of metal-oxide-semiconductor field-effect transistors (MOSFETs) are shrinking continually. However, in order to reduce short-channel effect (SCE) and hot-carrier effect, pocket and lightly doped drain (LDD) implants in MOSFETs were used. But, such measures also bring reverse short-channel effect (RSCE) and increase the channel resistance.
Consequently, in order to let device designers tune and predict the short channel behavior of nMOSFETs, so this research utilizes ISE TCAD version 10.0 to simulate nMOSFET characteristics and calculate Ion and Ioff for the gate lengths varied from long to short and for different energies and doses of pocket and LDD implants. At the same time, eight parameters are defined to characterize the obtained Ion / Ioff curves in terms of the gate length, and eight empirical models are also established in terms of the implant parameters. To further help the device designers in finding the desired implant parameters based on certain Ion and Ioff requirements, the methods of solving the empirical models are also provided and edited to be a mathematic program. In other words, using this work, device designers can input the characteristics of nMOSFETs’ Ion / Ioff, and then they can rapidly obtain desired process parameters (energies and doses of pocket and LDD implants).

並列關鍵字

MOSFET ； Gate Length ； Short-Channel Effect (SCE) ； Reverse Short-Channel Effect (RSCE) ； Pocket Implant ； Lightly Doped Drain (LDD) ； Threshold Voltage ； Drive Current ； Off-State Leakage Current

參考文獻

[24] 莊勝竣，“Using Simulation to Investigate RSCE and Vt Roll-off Controls for 90 nm Node MOSFETs,”碩士學位論文，國立臺北科技大學機電整合研究所，台北，2006。

[7] 高柏偉，“An Investigation on Hot Carrier Effect at Elevated Temperatures for pMOSFETs of 0.13um,”碩士學位論文，國立臺北科技大學機電整合研究所，台北，2006。

[10] 林文政，“Influence of Pocket Implant Angles on Digital and Analog Performances of Nano-MOSFETs,”碩士學位論文，國立臺北科技大學機電整合研究所，台北，2006。

[2] Jun-Wei Wu, Chih-Chang Cheng, Kai-Lin Chiu, Jyh-Chyurn Guo, Wai-Yi Lien, Chih-Sheng Chang, Gou-Wei Huang, and Tahui Wang, “Pocket Implantation Effect on Drain Current Flicker Noise in Analog nMOSFET Devices,”IEEE Trans. Electron Devices, Vol. 51, NO. 8, AUGUST 2004, pp. 1262-1266.

[3] Bin Yu, Clement H. J. Wann, Edward D. Nowak, Kenji Noda and Chenming Hu “Short-Channel Effect Improved by Lateral Channel-Engineering in Deep-Submicronmeter MOSFET’s,”IEEE Trans. Electron Devices, Vol. 44, NO. 4, 1997, pp. 627-634.