渦輪解碼器之SIP 產生器設計

The SIP Generator Design for Turbo Decoder

葉建良(Chien-Liang Yeh)

指導教授 ： 李文達

國立臺北科技大學/機電學院/電腦與通訊研究所/碩士(2005年)

摘要

近來的通訊系統中，渦輪解碼器已被廣泛應用，但因其被使用的領域及規格眾多且不盡相同，若以傳統的方式個別設計渦輪解碼器則會耗費大量人力及時間，不符合現代縮短Time to Market 的要求。因此在本論文提出一個新型具無反交錯器表架構的渦輪解碼器SIP 產生器，它不但提供了許多參數上的組合供使用者選擇外，也能提供自動效能分析模擬，產生訊雜比(SNR)與位元錯誤率(BER)的相對關係圖供通訊IC設計者評估此一渦輪解碼器的更錯效能，同時我們藉由分析交錯器與反交錯器之特性，改變記憶體的讀寫方式，進而只用一個單一交錯器表，就能達成交錯器與反交錯器的功能，有效的降低一半外部記憶體的需求量及減少記憶體資料的擾動，進而降低晶片的面積及功率。最後為了驗證可行性，我們實際使用TSMC 0.18 1p6m製程合成具1、2、4個MAP平行處理之渦輪解碼器晶片並作效能分析，實驗結果顯示在不影響解碼速率的情況下能有效的降低9.5%~15.6%的記憶體面積以及5.7%~11.1%的功率消耗。

關鍵字

渦輪解碼器 ； 交錯器 ； SIP 產生器

並列摘要

In communication system, turbo decoder is widely used nowaday. However, the specifications of turbo decoders are difference in various communication applications. It will cost lot of time and labor to design turbo decoder with traditional methods, which does not meet Time to Market requirement. In this thesis, we propose a De-interleaver free table turbo decoder SIP generator. This IP generator not only provides IC designer to generate a turbo decoder with configurable parameter but also the automatic performance simulation which produces the SNR and BER relation charts for IC designers to evaluate the error correction efficiency. Moreover, we analyzed the characteristics of interleaver and de-interleaver then re-arranged the extrinsic memory access order; thus only one interleaver table is needed to perform the function of interleaver and de-interleaver. This new architecture effectively reduces the extrinsic memory to half and shrinks the chip area and lowers the power consumption. Finally as to verify our SIP generator, we have synthesized the turbo decoder chips which consist 1, 2, and 4 parallel MAP decoders by TSMC 0.18 1p6m process, and also performed efficiency analysis. The experimental results show that the memory area is reduced by 9.5%~15.6% and power consumption by 5.7%~11.11% without degrading the decoding speed.

並列關鍵字

Turbo decoder ； Interleaver ； SIP Generator

參考文獻

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