由於多核心晶片的世代已經來臨,為了滿足多核心通訊的傳輸率,因此近幾年晶片網路(NoC)一直被視為解決多核心傳輸的問題。雖然高傳輸率被解決,但卻衍生出功率消耗、面積與死結等等問題。本論文提出時脈閘控架構設計來改善晶片網路的功率消耗與面積。當slot狀態處於Full(滿)或Empty(空)時,本方法對buffer進行clock-gating以減少功率消耗。根據實驗結果,當資料封包長度為10 bits時,本架構比IntelliBuffer架構的功率消耗可降低16.8%,面積減少45.9%以及時脈延遲減少2.7%。而與文獻[3]比較則功率消耗減少38%以及面積減少15.2%。當資料封包長度為18 bits時,本架構比IntelliBuffer架構的功率消耗可降低22.4%,面積減少40.9%以及時脈延遲減少2%。而與文獻[3]比較則功率消耗減少32.9%,面積減少13%以及時脈延遲減少2%。
The multicore system is more popular architecture in recently. The NoC (Network-on-Chip) architecture is proposed to solve the problem of high performance and throughput in a multicore system but it derived some problems such as of power consumption, area and deadlock, etc. This paper proposes a buffer clock-gating (BCG) architecture to improve the power consumption and area of buffers in Network-on-Chip. When buffer content is full or empty, the BCG uses clock-gating technology to gating buffer period to reduce power consumption. When data packet length is 10 bits: comparison with IntelliBuffer [2], the proposed method reduced 16.8% on power consumption, 45.9% on area and 2.7% on time delay and comparison with [3], the proposed method reduced 38% on power consumption and 15.2% on area. When data packet length is 18 bits: comparison with IntelliBuffer [2], the proposed method reduced 22.4% on power consumption, 40.9% on area and 2% on time delay and comparison with [3], the proposed method reduced 32.9% on power consumption, 13% on area and 2% on time delay.
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