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  • 學位論文

使用蛇行防護線與接地貫穿孔的最佳數量來抑制串音干擾

Suppression of Crosstalk Using Serpentine Guard Trace and Optimal Number of Grounded Vias

指導教授 : 黃文增 林丁丙
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摘要


近年來,數位電子產品朝向高頻、高速與低電壓操作,在此前提下,信號完整度在設計不良印刷電路板中將會被雜訊影響,進而造成系統不穩定。其中,串音干擾是一個主要影響信號完整度的雜訊來源。一般,串音干擾可以在侵略線與受害線之間加入一條防護線,另外,在防護線上面增加接地貫穿孔也能夠幫助減少串音干擾。然而,接地貫穿孔加在防護線上面時,對於頻率域中會造成共振現象,同時,在時域中會造成振鈴雜訊。因此,我們提出最佳接地貫穿孔數量與位置,能夠移動第一個共振點離開感興趣的頻帶並且減少振鈴雜訊。此方法提供適當的接地貫穿孔數量,增加電路繞線的彈性。從模擬結果指出使用最佳接地貫穿孔數量與位置跟沒有防護線的架構比較在時間領域中,近、遠端串音干擾分別減少27.65%與31.63%;進一步,根據實驗的結果指出使用最佳接地貫穿孔數量與位置跟沒有防護線的架構比較在時間領域(頻率領域)中,近、遠端串音干擾分別減少34.49% (2.1dB)與37.55% (3.3dB)。同時,使用兩個匹配的終端電阻的蜿蜒防護線方法被用以減少遠端串音干擾,但是它卻忽略了由近端串音干擾產生的問題;因此我們提出了蜿蜒防護線貫穿孔的方法,這個方法是將接地貫穿孔加在蜿蜒防護線上面適當的位置,然後我們調整個水平與垂直的比例,能夠減少近、遠端串音干擾。更進一步,蜿蜒防護線貫穿孔使用接地貫穿孔取代終端電阻,所以蜿蜒防護線貫穿孔的兩個終端上面不需要任何額外的元件。在頻率領域中,模擬(測量)的結果中顯示蜿蜒防護線貫穿孔與沒有防護線的架構比較於近端串音干擾減少3.7 (7.65) dB,遠端串音干擾減少5.11 (7.22)dB,然後與蜿蜒防護線比較於近端串音干擾減少0.83 (1.6) dB,遠端串音干擾減少0.1 (1.98) dB;在時間領域中,模擬(測量)的結果中顯示蜿蜒防護線貫穿孔與沒有防護線的架構比較於近端串音干擾減少34.67% (49.8%),遠端串音干擾減少46.78% (56.52%),然後與蜿蜒防護線比較於近端串音干擾減少27.5% (26.65%),遠端串音干擾減少6.91% (24.8%)。由模擬與實驗證明,提出的方法能夠有效的減少串音干擾;當印刷電路板設計時,使用接地貫穿孔是簡單且不昂貴的策略,因此我們的方法適合在實際工程應用上使用。

並列摘要


During recent years, modern electronic products are increasingly based on high-speed and high-density circuitry operating at lower voltages. With such designs, the signal integrity (SI) in a poor printed circuit board (PCB) layout is affected by noise and may become unstable. Crosstalk is a major source of noise that interferes with SI. Generally, the crosstalk can be reduced by adding a guard trace between the victim and aggressor areas of the circuit. In addition, grounded vias can be added to the guard trace to help reduce the crosstalk. However, the grounded vias in the guard trace induced the resonance in the frequency domain and the ringing noise in the time domain. Hence, we propose the optimal number and location of the grounded vias to shift the first resonance point away bandwidth of interest and to reduce ringing noise. The proposed method offers appropriate number of grounded vias to increase the flexibility on the circuit routing. The simulation results indicated that the optimal number and location of grounded vias in the guard trace could reduce the near-end crosstalk (NEXT) and far-end crosstalk (FEXT) by 27.65% and 31.63% compared to the without guard trace (WOGT) approach in the time domain, respectively. Moreover, the experimental results indicated that the optimal number and location of grounded vias in the guard trace could reduce NEXT and FEXT by 34.49% (2.1 dB) and 37.55% (3.3 dB) compared to the WOGT approach in the time domain (frequency domain), respectively. The serpentine guard trace (SGT) approach has been used to reduce FEXT using two terminal matching resistors on SGT between the aggressor and victim, but it neglects interference caused by NEXT. Therefore, we propose the SGT via (SGTV) approach in which grounded vias are added to the SGT at appropriate locations, and the ratio between the lengths of the horizontal and vertical sections of the guard trace is adjusted to minimize NEXT and FEXT. Furthermore, SGTV used the grounded vias to replace the terminated resisters; it does not need extra components in the two terminations of SGTV. In the frequency domain, the simulated (measured) results indicated that SGTV could improve NEXT by 3.7 (7.65) dB compared to the WOGT approach and 0.83 (1.6) dB compared to the SGT approach. The equivalent figures for FEXT were 5.11 (7.22) and 0.1 (1.98) dB, respectively. In the time domain, the simulated (measured) results indicated that SGTV improved NEXT by 34.67% (49.8%) compared to the WOGT approach and 27.5% (26.65%) compared to the SGT approach. The equivalent figures for FEXT were 46.78% (56.52%) and 6.91% (24.8%), respectively. Based the simulation and experimental results, the proposed methods can reduce the crosstalk effectively. For the PCB design, using the grounded vias is simple and inexpensive strategy; hence, our methods could suitable for practical application.

參考文獻


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