高速用PCB之繞線策略

High-speed PCB Routing Strategy

陳泳昌(Yung-Chang Chen)

指導教授 ： 方志鵬

國立臺北科技大學/電資學院/電機工程系研究所/碩士(2008年)

摘要

高速用印刷電路板(PCB，Printed Circuit Board)之繞線(Routing)是當前數位電路設計相當重要的課題。良好的PCB布局(Placement)與繞線不但可以獲得好的信號品質，進而提升PCB的工作頻率，甚至縮減PCB尺寸，降低成本。
在嵌入式系統(Embedded System)中，數位電路的設計最常利用FPGA/CPLD作為核心，且由於FPGA/CPLD具有可交換接腳(Pin)的特性，因此本論文在讀取電路的網表(Netlist)後，應用倒轉值(Inversion Value)和模擬退火演算法(SA, Simulated Annealing Algorithm)來解析繞線的複雜度，在不影響原本電路功能下重組繞線，使PCB繞線複雜度降至最低，最後寫回網表。
藉由Mentor的PADS這套Layout工具，我們把最初的網表和經由本論文提出方法改變的網表一起匯入到PADS作為比較，可以明顯的看出改變後的網表繞線複雜度大為降低。由此可以得知本論文提出一個有效的方法改進繞線擁擠度，藉此實現設計高速PCB的需求。

關鍵字

高速 ； 繞線 ； 模擬退火 ； 印刷電路板

並列摘要

High-speed Printing Circuit Board (PCB) routing is one of the most important issues in current digital circuit design. A good PCB placement and routing not only can help to gain good quality on signals, but also can enhance the operating frequency, furthermore, it can lower the production cost even by downsizing the PCB.
In embedded system of digital circuits, both CPLD and FPGA are frequently used as the core of design. Since both CPLD/FPGA are pin-exchangeable, this research analyzes the complexity of routing using both Inversion Value and Simulated Annealing (SA) algorithm after accessing the circuit netlist. Routing rearrangement was attempted without impacting on the function of the original circuits so that carried the PCB routing complexity to its lowest extent, and finally wrote it back to the netlist.
Comparing the imported-unmodified netlist to the modified using Mentor's PADS, the routing complexity of the modified netlist that has been reduced is significant. Therefore an effective method of reducing the complexity of routing rearrangement has been proposed by this thesis, which may be used in fulfilling the design requirement of high-speed PCB system.

並列關鍵字

High-speed ； Inversion Value ； Simulated Annealing ； PCB ； Routing

參考文獻

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