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  • 學位論文

不同氮化退火溫度下對High-k堆疊/金屬閘極nMOSFETs之特性分析與熱載子效應探討

Electrical Characteristics and Hot-Carrier Effect of Stacked High-k/Metal-Gate nMOSFETs under Nitridation Annealing Temperatures

指導教授 : 黃恆盛 陳雙源
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摘要


在45奈米世代及以下的製程,使用高介電材料/金屬閘極(HK/MG)堆疊技術結合應變矽技術之MOS元件,可以解決在閘極介電層厚度微縮的情況下,所造成較大的閘極漏電流問題,並且可以提升驅動電流。過去的研究指出,閘極介電層沉積之後,在退火中添加氮氣可以部分修補介電層的缺陷,進而改善介電層的品質,但極少有探討去耦合電漿氮化(DPN)退火於不同退火溫度下,對閘極電介層之熱載子效應與基本電性的影響,因此,此方面為本論文研究重點。 本研究是針對聯華電子所提供的28奈米MOSFET元件作分析探討。其閘極電介層是利用原子層沉積技術(ALD)製作,其閘極介電質乃選用氧化鋯鉿(HfZrOx)的高介電材料。在此研究中,量測實驗參數包括不同通道長度和加熱溫度;再依實驗數據,進行統整與實驗結果分析,並探討不同的退火製程溫度和不同氮化環境下之間的元件電特性差異。 研究結果顯示,在不同的DPN氮化退火溫度下,其基本特性上並沒有明顯的差異。在通道熱載子(CHC)的加電壓測試條件下,短通道(0.03?m)元件劣化程度比長通道(1?m)來得明顯,其中,於量測溫度125℃下,以8%含氮量、退火溫度為900℃的nMOSFET劣化程度最為嚴重,這是歸因於較高的退火溫度下,較厚的介面介電層的形成和結晶化。

並列摘要


Since 45nm process generation and beyond, high-k/metal-gate (HK/MG) combining strain engineering technology for nano-scale MOSFETs incorporated into the conventional CMOS process is available and promising to increase the drive current. In the past, after gate dielectric deposition, the annealing process with nitrogen gas was commonly adopted to repair the existence of defects in gate dielectric and therefore improve the quality of interfacial layer in MOSFETs. However, few published researches discussed the nitridation effect of decoupled plasma nitridation (DPN) process with the hot-carrier effect and electrical characteristics at different annealing temperatures. In this study, I focus on these points and try to establish these relationships. In this work, the tested 28nm wafers came from UMC. The hafnium-based gate dielectric with a profile of HfOx/ZrOy/HfOz (HZH) was deposited with atomic layer deposition (ALD) technology. The experimental parameters include the different channel lengths and stress temperatures. Consequently, through the statistical and analytical analysis of experimental data, the nitridation effect with annealing temperatures reflecting the various results of device electrical characteristics are exposed in this thesis. After the analysis, the annealing temperatures after DPN treatments do not obviously impact the device performance. Owing to the stronger horizontal electrical field, the degradation of short channel nMOSFETs with L=0.03?m in channel hot-carrier (CHC) stress is more serious than that with L=1?m. Additionally, for the identical L, the worst degradation of nMOSFETs with CHC test is the samples of 8% N2 concentration and 900℃ annealing temperature stressed at 125℃. This may attribute to the formation of thicker oxide interfacial layer (IL) and was annealed cause crystallization.

參考文獻


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