使用隨機存取掃描設計以減少測試時間及功率消耗

在超大型積體電路測試中，測試時所耗費的功率以及花費的時間是目前所面臨的議題。電路所耗費的功率消耗遠大於正常模式，因此受測電路的正反器會被修改為掃描細胞，每一個掃描細胞的輸入端會連接到下一個掃描細胞的輸入端，而串聯成一個掃描鍊，當電路的測試資料輸入時可再掃描鍊得到測試結果的抓取。在測試期間資料將以一個位元為單位，依序輸入至掃描鍊中，相同時間下前一個測試結果也會經由掃描鍊輸出端送出觀察。在本論文中，我們將以降低測試過程中所造成的大量功率的耗費(reduce test power dissipation)作為我們研究的目標。在這篇論文中引用了隨機存取掃描設計硬體架構(Random Access Scan Architecture)可以大量減少在電路測試時資料的讀取與寫入時間，並且利用非對稱性旅行者推銷員演算法(Asymmetric Traveling Salesman Problem Algorithm)找出掃描鍊在擷取所時花費最少成本的過渡態(transition)將測試資料順序重排，使電路在測試過程中產生的過渡態可以獲得大幅的降低。此外在傳統的掃描鍊硬體架構中，利用有效的演算法找出有利於硬體下的掃描鍊群組，透過資料重排後的輸入與輸出的掃瞄細胞結果皆記錄成表格，再將測式資料對應影響的掃描細胞鍊建出一個完全有向權重關聯圖，找出一筆資料所動用到最多的掃描細胞群組，達到減少測試時時脈(clock)浪費，達成減少測試時所需要耗費的時間。由實驗結果中採用ISACS89的測試電路，透過重排測試資料後，發現掃描細胞平均可減少28.1%，之後研究再將有利於隨機存取掃描設計硬體架構下對掃描細胞分群，以達到減少時脈的消耗，來提升測試時電路的良率與效率，最後，經由本實驗研究結果中可觀察出，利用兩種不同的求解(solver)後，可有效成功減少1.5至3倍的測試功率消耗。

關鍵字

隨機存取掃描設計硬體架構；非對稱性旅行者推銷員演算法

並列摘要

Traditional testing research for testing VLSI circuits consume testing time and power. In fact, circuit model can be divided into two modes. One is normal mode, the other is test mode. While on the test mode, it wasted more power than normal mode. This paper presents an architecture modification method for reducing power dissipation during test application for a full-scan circuit. Therefore, Random access scan (RAS) for scan testing has lower test application time, low power dissipation, and low test data volume compared to standard serial scan chain based design. The problem can be reduced to an asymmetric traveling salesman problem (ATSP) that found the asymmetric shortest Hamiltonian path for a graph constructed as follows. Random access scan reduces test application time even further by exploiting the parallelism among the clusters and performing write operations on multiple bits. In our experiment results for ISCAS-89 benchmark circuits, our proposed method could reduce transition count and power consumption during scan testing of given ordering test vectors by 28.1%. In addition, Finally, on benchmark circuits show that we can decrease the reduction rate in the range of 1.01x to 2.4x by using two different solvers, and write test data volume reduction.

並列關鍵字

RAS ； ATSP

參考文獻

[4] Adiga, R, Arpit, G, Singh, V, Saluja, K.K, Fujiwara, H, Singh, A.D, “On Minimization of Test Application Time for RAS,” in VLSI Design, 2010. VLSID '10. 23rd International Conference, pp 393 – 398, 2010.

[1] Dong Hyun Baik, Saluja, K.K, “Progressive Random Access Scan: A simultaneous solution to test power, test data volume and test time,” in Test Conference, 2005. Proceedings. ITC 2005. IEEE International, pp. – 368, 2005.

[2] Ghosh, I, Raghunathan, A, Jha, N.K, “A Design-for-Testability Technique for Register-Transfer Level Circuits Using Control Data Flow Extraction,” in Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions, vol. 17, pp. 706 – 723, 1998.

[3] Abu-Issa, A.S, Quigley, S.F, “Multi-degree smoother for low power consumption in single and multiple scan-chains BIST,” in Quality Electronic Design (ISQED), 2010 11th International Symposium, pp. 689 – 696, 2010.

[5] Yao, C, Saluja, K.K, Sinkar, A.A, “WOR-BIST A Complete Test Solution for Designs Meeting Power, Area and Performance Requirements,” in VLSI Design, 2009 22nd International Conference, pp 479 – 484, 2009.

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使用隨機存取掃描設計以減少測試時間及功率消耗

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