針對多位元正反器合併之寬裕時間分配

Slack Budgeting for Multi-Bit Flip-Flop Merging

呂嘉杰(Chia-Chieh Lu)

指導教授 ： 林榮彬

元智大學/資訊學院/資訊工程學系/碩士(2012年)

https://doi.org/10.6838/YZU.2012.00359

摘要

近來，有許多針對擺置後的多位元正反器合併方法的研究被提出。在多位元正反器的合併過程中，我們需要寬裕時間來決定正反器在合併過程中的可移動範圍，進而得之哪些正反器可以合併。然而，目前絕大多數的多位元正反器合併的研究都僅僅針對合併方法探討，而正反器輸入輸出上的寬裕時間都只假設為已知。在本篇論文中，我們提出一個有彈性的針對多位元正反器合併之寬裕時間分配方法，這個方法可以在各種不同的設計需求下順利的分配寬裕時間，使合併對電路效率的影響降至最低。同時，我們也提出了一個寬裕時間對繞線長度的轉換方法。這個寬裕時間對繞線長度的轉換方法有考量到許多先前許多研究都沒有注意到的時序延遲增加，可以使合併時正反器可移動範圍的判斷各符合實際的時序限制。實驗結果顯示，我們的合併方法平均可以降低32% 的 clock tree功率消耗、3% 的總電路功率消耗與2.28% 的電路面積。電路的面積以及功率消耗。合併後的電路其最糟寬裕時間與合併前相比平均只有降低10%，而且絕大多數的最糟寬裕時間都是正數。

關鍵字

寬裕時間分配 ； 多位元正反器 ； 多位元正反器合併 ； 時序分析 ； 低功率消耗 ； 時鐘網路

並列摘要

Recently, many post-placement Multi-Bit Flip-Flop merging approaches are proposed. When merging flip-flops, we need timing slack on input/output of flip-flops to obtain movable region of flip-flops and determine which flip-flops can be merged. However, most Multi-Bit Flip-Flop merging studies assume timing slack are given and can be easily translated into the corresponding wire length. In this thesis, we propose a flexible slack budgeting approach for Multi-Bit Flip-Flop merging. The slack budgeting approach can generate more accurate slack budget by considering wiring topology and the changes of delay on flip-flops output due to merging. We also propose an approach to converting timing slack into wire length. The conversion considers the influence of wire length on the delay of driving cells so that a more accurate movable region can be determined for flop-flop. Experimental results show that our merging approach can reduce clock tree power up by 32%, power by 3%, and chip area by 2.28% on average. Moreover, worst slack on average decrease by 10%.

並列關鍵字

timing analysis ； low power ； clock network ； Slack budgeting ； Multi-bit flip-flop ； Multi-bit flip-flop merging

參考文獻

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