適合高效能及低功率處理器設計的合成技術

Synthesis Techniques for High-Performance and Low-Power Processor Designs

郭武安(Wu-an Kuo)

指導教授 ： 吳中浩 ； 黃婷婷

國立清華大學/電機資訊學院/資訊工程學系/博士(2006年)

https://doi.org/10.6843/NTHU.2006.00079

摘要

積體電路製程的演進使得元件尺寸越來越小。在元件縮小的同時，越來越多的元件可以放入單一的晶片中。為了讓晶片中的大量元件共同運作，以處理器為主的設計架構已成為主流。對於如何設計處理器，效能及功率消耗為兩個主要的議題，這兩個議題與指令的完成相關性非常高。要完成一個指令，抓取、解碼及執行是主要的三個步驟。我們將針對這三個步驟提出方法來改善處理器的效能及功率消耗。
首先，針對抓取的步驟。因為製程的演進，使得兩條導線的距離越來越短，隨之而來的串音問題，使得導線上的延遲變的十分嚴重。我們發現指令匯流排上的傳輸資料可以在編譯時就可以加以控制，所以提出兩個編譯器演算法──指令重新排程及暫存器更名，來消除指令匯流排上的串音效應，進而改善指令匯流排的效能。
其次，對解碼的步驟來說，我們發現指令執行的機率不是平均的。這表示在大部分的時候，我們不需要實現整個指令解碼器，來為指令解碼。藉由分析程式執行的序列，我們將指令解碼器分割成數個子解碼器。在大部分的時候，只有一個子解碼器在工作，因而改善了功率消耗。
最後，對執行的步驟來說，乘法指令一向指令集中消耗功率大及執行時間長的部分。我們以一個長度可變的雙乘法器結構，提出一個產生乘法指令的方法，來減少特殊應用指令處理器的功率消耗。這方法可以分析乘法指令的執行順序及乘法運算元的有效長度，來減少因為重覆位元的功率消耗。

關鍵字

高效能 ； 低功率 ； 處理器 ； 串音 ； 編譯器 ； 指令匯流排 ； 指令解碼器 ； 乘法器

並列摘要

Significant advances in VLSI process technology have scaled the feature size down. As the transistor size shrinking, more and more transistors can be integrated into a single chip. To make large number of components in a chip working together, processor-based design methods have become one of the best choices. In a processor design, power consumption and performance are two important issues. The power and performance issues are related to the execution of an instruction. During the execution of an instruction, three main steps are fetching, decoding, and executing. We will propose techniques to improve performance and power in these three steps.
First, for the step of fetching instructions, because the advances of technology shorten the distances between wires, the crosstalk problem has affected the wire delay seriously. Since the data sequences on an instruction bus are known during the compile time, we present two compiler algorithms, rescheduling and renaming, for performance improvement by eliminating crosstalk effects on an instruction bus.
Second, for the step of decoding instructions, we found that the execution frequency of instructions is uneven. It means that in most of time, we need not utilize the whole instruction decoder to decode instructions. By tracing program execution sequences, we decompose the instruction decoder into several coupling sub-decoders. For most of time, only one sub-decoder is activated and the power is minimized.
Finally, for the step of executing instructions, the multiplication is the most power consuming operation among all operations in an instruction set. Based on a dual-&-configurable-multiplier structure, our proposed method devises a multiplication instruction-set for low-power ASIPs. Our method exploits the execution sequences of multiplication instructions and effective bit-widths of variables to reduce power consumed by redundant multiplication bits.

並列關鍵字

High performance ； Low power ； Processor ； Crosstalk ； Compiler ； Instruction bus ； Instruction decoder ； Multiplier