單晶片系統在三維積體電路上之測試架構與方法

SOC Test Architecture and Method for 3D ICs

駱致彥(Chih-Yen Lo)

指導教授 ： 吳誠文

國立清華大學/電機資訊學院/電機工程學系/博士(2010年)

摘要

中文摘要 藉著製程技術持續地微縮，半導體產業在以往的數十年裡，憑著維持摩爾定律之姿，不斷地滿足市場對於電子產品的在功能性及其效能上毫無止境的需求。然而直到最近，它們也不得不面臨在CMOS技術上持續微縮的瓶頸與在研發單晶片系統上成本的持續高漲。牽涉到橫跨整體電路之長導線的信號延遲及功率消耗，儼然成為在合理成本下持續提升電路效能的主要障礙。藉著在垂直方向堆疊晶片且彼此間使用穿矽孔作訊號連結，三維整合技術有效地解決上述問題。然而，該項技術距離其在商品上的應用，仍有些障礙等待解決。其中，與三維積體電路測試相關的工具與方法，被視為其中首要的挑戰。 在本篇論文中，我們聚焦在三維積體電路中測試整合的相關問題。我們提出一具備彈性與可延展性的測試架構，以支援三維積體電路在其堆疊前後所需的測試。該架構被稱為TACS-3D[1]。為要降低三維積體電路的測試成本，我們在所提的測試架構下，針對測試所需的TAM與控制訊號與予最佳化，以降低所使用之晶圓測試探針與穿矽孔的數目。就三維積體電路在堆疊前的測試而言，TACS-3D繼承了我們從前為了測試單晶片系統中嵌入式核心電路而研發之測試架構(TACS)的一切優點。除了針對傳統stuck-at錯誤的測試圖樣，造成時間延遲相關之瑕疵也一併考慮在它所支援的測試特性中。因為TACS本身針對其所需之測試探針數目就已經藉著共用一些控制訊號以進行最佳化，所以 TACS-3D在三維積體電路堆疊前，以晶圓探測尋找KGD時，照樣可以減少額外所需用以承載晶圓測試之探針的面積。為要在三維積體電路堆疊後的測試中，有效地重複使用其用在堆疊前的測試相關電路，我們提出了一套創新的機制以聯絡座落在三維積體電路的各層中間之測試電路。在所提出的機制之下，三維積體電路的層數並不影響整體所需之控制測試訊號的數目。並且讓大部分的穿矽孔在進行測試時，保留作為傳輸測試資料和結果之用。所以在這情況下，我們可以期待有較短的整體測試時間。此外，藉著整合許多異質性的可測試性設計方法(諸如為著在三維積體電路中的邏輯電路、記憶體電路、以及穿矽孔的測試)，我們減輕了在三維積體電路堆疊後的測試中，可能出現之測試探針與測試穿矽孔擁塞的情形。 TACS-3D不僅在邏輯電路的測試上維持原本TACS的優勢，更支援了與自我測試電路相關的測試方法(例如：記憶體自我測試電路)。此外，憑著過去我們將支援邏輯自我測試電路的TACS，移轉到低成本的HOY無限測試系統之相關經驗，TACS-3D也照樣可以具備相關的特性。另外，針對製造三維積體電路過程中所引進的新製程，有可能在垂直的連接線上造成新的瑕疵。我們重複使用1500測試包裹電路來對穿矽孔進行相關的測試。藉著將接連到垂直連接線的所有WBR cell串接成為UTC或是LTC，我們可以減少額外為穿矽孔測試所需增加的測試電路。 最後，我們以一個具有四個加密處理器的網路安全處理器為例子，討論當二維電路轉換為三維電路時在測試方面的影響。藉著採用所提出的TACS-3D測試架構，不管是在面積或是測試時間上，都僅僅增加小於0.4%的額外代價。此外在第二個實驗裡，在使用相同數目的測試穿矽孔與測試探針之條件下，比起直接將各層的控制電路以穿矽孔連接到其最底層之輸出入端的方法，TACS-3D最多可以達到縮短54%的整體測試時間。

關鍵字

三維積體電路測試 ； 測試架構 ； 單晶片測試 ； 穿矽孔測試 ； 測試整合 ； 無線測試系統

並列摘要

Abstract

By continuous technology scaling, the semiconductor industry has kept up with the Moore’s Law
for decades to satisfy the endless demands in both functionality and performance of electronic
devices. But until recently, they have to face the bottleneck of CMOS technology scaling and
soaring system-on-chip (SOC) development cost. The delay and power consumption issues of
global interconnects become the main barriers of further performance progress under allowable
cost. By stacking dies vertically and connecting them with through-silicon-vias (TSVs), threedimensional
(3D) integration solves this problem effectively. However, there are still obstacles
to its commercial application. Tools and methodologies for 3D-IC testing are regarded as the
number-one challenge.

We focus on the problem of test integration in 3D ICs. A flexible and scalable architecture [1]
supporting both pre-bond [2] and post-bond tests for core-based 3D ICs is proposed. It is named
as Test Access Control System for 3D ICs (TACS-3D) [1]. In order to reduce the testing cost
of the 3D IC, not only test access mechanism (TAM) but also the control signals are optimized
to reduce the usage of test pins and TSVs for 3D-IC testing. For the pre-bond test in the 3D
IC, it is similar to traditional SOC testing. TACS-3D inherits the advantage of our previously
developed test architecture named Test Access Control System (TACS) to provide test access and
related control for embedded core testing. In addition to the patterns for traditional stuck-at faults,
the timing related defects are also considered in its test features. Since TACS has optimized the
test pin usage by sharing the required test control signals, TACS-3D can minimize the extra pads
required for finding Known-Good Dies (KGDs) in wafer probing. To highly reuse pre-bond test
circuits in the post-bond test stage, an innovative linking mechanism is proposed for sharing TSVs
and test pins between embedded cores in multiple layers. No matter how many layers are there
in the 3D IC, only 5-bit signals are sufficient for test control. A large portion of TSVs and test
pins can be reserved for data application; therefore smaller total test time is expected. In addition,
integration of heterogeneous DFT methods for logic, memory, and TSV testing in the 3D IC further
alleviates the congestion of test pins and TSVs for post-bond test.

For logic testing, TACS-3D retains the robustness of TACS that features the IEEE 1500 Wrapper
Control, hierarchical test control, at-speed test (for transition faults), functional and scan test,
heterogeneous test protocols. In addition, memory built-in self-test (MBIST) is taken as examples
to support BIST-based methods in TACS-3D. Furthermore, the way to support logic built-in
self-test (LBIST) can be applied through our proposed low-cost testers, i.e., the HOY wireless test
system. For the newly introduced defects in the bonding processes during 3D-IC construction,
TACS-3D also reuses 1500 Test Wrapper to do TSV testing. All the Wrapper Boundary Register
(WBR) cells of the embedded cores whose corresponding inputs (outputs) are from (to) the upper
layer of the 3D IC through TSVs are reconfigured to be the Upper TSV chains. In a similar way,
all of them related to the lower layer of the 3D IC through TSVs are reconfigured to be the Lower
TSV Chains. These two types of scan chains are only configured during the TSV testing. All above
techniques contribute to the reduction of TSVs and test pins for 3D-IC testing.

A test chip composed of a Network-Security-Processor (NSP) platform with four Crypto Processors
(CPs) is taken as an example. We discuss the related effects about testing when transferring
design from 2D to 3D. By adopting the proposed test architecture for 3D IC, less than 0.4% test
overhead increases in both area and time between 2D and 3D test cases. The experimental results
also reveal up to 54% test time improvement compared with the method of direct access.

並列關鍵字

3D-IC test ； test architecture ； SOC test ； TSV test ； test integration ； wireless test system

參考文獻

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[62] C.-P. Su, C.-H. Wang, K.-L. Cheng, C.-T. Huang, and C.-W. Wu, “Design and test of a

Soussan, R. Cartuyvels, E. Beyne, S. Biesemans, and B. Swinnen, “3D stacked IC demonstration